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2 1 - s3-c9484/c9488/f9488 - 092003 user's manual s3c9484/c9488/f9488 8- b it cmos microcontroller revision 1
s3c9484/c9488/f9488 product overview 1- 1 1 product overview s3c9-series microcontrollers samsung's sam88rcri family of 8-bit single-chip cmos microcontrollers offers a fast and efficient cpu, a wide range of integrated peripherals, and various mask-programmable rom sizes. a address/data bus architecture and a large number of bit-configurable i/o ports provide a flexible programming environment for applications with varied memory and i/o requirements. timer/counters with selectable operating modes are included to support real-time operations. s3c9484/c9488/f9488 microcontroller the s3c9484/c9488/f9488 single-chip cmos microcontrollers are fabricated using the highly advanced cmos process technology based on samsung?s latest cpu architecture. the s3c9484 is a microcontroller with a 4k-byte mask-programmable rom embedded. the s3c9488 is a microcontroller with a 8k-byte mask-programmable rom embedded. the S3F9488 is a microcontroller with a 8k-byte multi time programmable rom embedded. using a proven modular design approach, samsung engineers have successfully developed the s3c9484/c9488/f9488 by integrating the following peripheral modules with the powerful sam88 rcri core: ? five configurable i/o ports (38 pins) with 8-pin led direct drive and lcd display ? ten interrupt sources with one vector an d one interrupt level ? one watchdog timer function with two source clock (basic timer overflow and internal rc oscillator) ? one 8-bit basic timer for oscillation stabilization ? watch timer for real time clock ? two 8-bit timer/counter with time interval, pwm, and capture mode ? analog to digital converter with 9 input channels and 10-bit resolution ? one asynchronous uart the s3c9484/c9488/f9488 microcontroller is ideal for use in a wide range of home applications requiring simple timer/counter, adc, led or lcd display with adc application, etc. they are currently available in 32-pin sop/sdip, 42-pin sdip and 44-pin qfp package. mtp the S3F9488 has on-chip 8-kbyte multi time programmable (mtp) rom instead of masked rom. the S3F9488 is fully compatible to the s3c9488, in function, in d.c. electrical characteristics and in pin configuration.
product overview s3 c9484/c9488/f9488 1- 2 features cpu sam88rcri cpu core memory 208-byte general purpose register (ram) 4/8-kbyte internal mask program memory 8-kbyte internal multi time program memory (S3F9488) oscillation sources crystal, ceramic, rc cpu clock divider (1/1, 1/2, 1/8, 1/16) instruction set 41 instructions idle and stop instructions added for power- down modes instruction execution time 500 ns at 8-mhz f osc (minimum) interrupts 10 interrupt sources with one vector / one level i/o ports total 38 bit-programmable pins (44qfp) total 36 bit-programmable pins (42sdip) total 26 bit-programmable pins (32sdip/32sop) basic timer one programmable 8-bit basic timer (bt) for oscillation stabilization control 8bit timers a/b one 8-bit timer/counter ( timer a ) with three operating modes; interval mode, capture mode and pwm mode. one 8-bit timer/counter ( timer b ) carrier frequency (or pwm) generator. watch timer real-time and interval time measurement. four frequency output to buz pin. clock generation for lcd. lcd controller/driver (optional) 8 com 19 seg (max 19 digit) 4 com 19 seg (max 8 digit) a/d converter nine analog input channels 12.5us conversion speed at 4mhz f adc clock. asynchronous uart programmable baud rate generator support serial data transmit/receive operations with 8-bit, 9-bit uart watchdog timer two oscillation sources selection (by smart option) safety work for noise interference low voltage reset (lvr) low voltage check to make system reset v lvr = 2.6v/3.3v/3.9v voltage detector for indication voltage detector to indicate specific voltage. s/w control (2.4v, 2.7v, 3.3v, 3.9v) operating temperature range ?25 c to + 85 c operating voltage range 2.2v to 5.5 v at 4 mhz f osc 2.7v to 5.5 v at 8 mhz f osc package type 32-pin sdip, 32-pin sop 42-pin sdip, 44-pin qfp smart option low voltage reset(lvr) level and enable/disable are at your hardwired option. i/o port (p0.0- p0.2/p3.3-p3.6) mode selection at reset. watchdog timer oscillator selection.
s3c9484/c9488/f9488 product overview 1- 3 block diagram i/o port and interrupt control sam88rcri cpu 8-kbyte rom 208-byte ram osc/reset 8-bit basic timer 8-bit timer /counter a watchdog timer with rc oscillator 8-bit timer /counter b watch timer port 0 port 1 a/d port 2 lcd driver uart com0-7 seg0-18 p2.0-p2.7 (seg3-10) p4.0-p4.6 (seg0-2, seg11-14) p3.0-p3.6 (seg15-18, int0-3) x in , xt in x o ut , xt out reset (p0.2) taout(p3.4) tack(p3.5) tbpwm(p1.0) buz(p1.1) p1.0-p1.7 (adc0-3, com0-3) p0.0-p0.7 (adc4-8/com4-7) av ref port 4 port 3 txd(p3.2) rxd(p3.1) tacap(p3.6) figure 1-1. s3c9484/c9488/f9488 block diagram
product overview s3 c9484/c9488/f9488 1- 4 pin assignment p 2 . 3 / s e g 6 p 2 . 2 / s e g 5 p 2 . 1 / s e g 4 p 2 . 0 / s e g 3 p 4 . 2 / s e g 2 p 4 . 1 / s e g 1 p 4 . 0 / s e g 0 p 1 . 7 / c o m 0 p 1 . 6 / c o m 1 p 1 . 5 / c o m 2 p 1 . 4 / c o m 3 seg7/p2.4 seg8/p2.5 seg9/p2.6 seg10/p2.7 seg11/p4.3 seg12/p4.4 seg13/p4.5 seg14/p4.6 seg15/p3.0 seg16/rxd/p3.1 seg17/txd/p3.2 s3c9484 s3c9488 S3F9488 (top view) (44-qfp) 34 35 36 37 38 39 40 41 42 43 44 3 3 3 2 3 1 3 0 2 9 2 8 2 7 2 6 2 5 2 4 2 3 p1.3/adc0 p1.2/adc1 p1.1/adc2/buz p1.0/adc3/tbpwm p0.7/com4/adc4 p0.6/com5/adc5 p0.5/com6/adc6 av ref p0.4/com7/adc7 p0.3/adc8 p0.2/resetb 22 21 20 19 18 17 16 15 14 13 12 s e g 1 8 / i n t 0 / p 3 . 3 t a o u t / i n t 1 / p 3 . 4 t a c k / i n t 2 / p 3 . 5 t a c a p / i n t 3 / p 3 . 6 v d d x o u t t e s t x t i n / p 0 . 0 x t o u t / p 0 . 1 1 2 3 4 5 6 7 8 9 1 0 1 1 v s s x i n figure 1-2. s3c9484/c9488/f9488 pin assignment (44-qfp)
s3c9484/c9488/f9488 product overview 1- 5 seg12/p4.4 seg13/p4.5 seg14/p4.6 seg15/p3.0 seg16/rxd/p3.1 seg17/txd/p3.2 seg18/int0/p3.3 taout/int1/p3.4 tack/int2/p3.5 tacap/int3/p3.6 v dd v ss x out x in test xt in /p0.0 xt out /p0.1 resetb/p0.2 av ref com6/adc6/p0.5 com5/adc5/p0.6 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 p4.3/seg11 p2.7/seg10 p2.6/seg9 p2.5/seg8 p2.4/seg7 p2.3/seg6 p2.2/seg5 p2.1/seg4 p2.0/seg3 p4.2/seg2 p4.1/seg1 p4.0/seg0 p1.7/com0 p1.6/com1 p1.5/com2 p1.4/com3 p1.3/adc0 p1.2/adc1 p1.1/adc2/buz p1.0/adc3/tbpwm p0.7/adc4/com4 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 24 23 22 s3c9484 s3c9488 S3F9488 (top view) 42-sdip figure 1-3. s3c9484/c9488/f9488 pin assignment (42-sdip)
product overview s3 c9484/c9488/f9488 1- 6 v ss test xt in /p0.0 xt out /p0.1 resetb/p0.2 av ref adc3/tbpwm/p1.0 buz/adc2/p1.1 adc1/p1.2 adc0/p1.3 com3/p1.4 com2/p1.5 com1/p1.6 com0/p1.7 s3c9484 s3c9488 S3F9488 (top view) 32-sop 32-sdip 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 v dd p3.6/int3/tacap p3.5/int2/tack p3.4/int1/taout p3.3/int0/seg18 p3.2/txd/seg17 p3.1/rxd/seg16 p3.0/seg15 p2.7/seg10 p2.6/seg9 p2.5/seg8 p2.4/seg7 p2.3/seg6 p2.2/seg5 p2.1/seg4 p2.0/seg3 32 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 x out x in figure 1-4. s3c9484/c9488/f9488 pin assignment (32-sop/sdip)
s3c9484/c9488/f9488 product overview 1- 7 pin descriptions table 1-1. pin descriptions of 44-qfp and 42-sdip pin names pin type pin description circuit type 44 pin no. 42 pin no. shared functions p0.0, p0.1 p0.2 p0.3 p0.4 p0.5 p0.6 p0.7 i/o i/o port with bit-programmable pins. configurable to input or push-pull output mode. pull-up resistors can be assigned by software. pins can also be assigned individually as alternative function pins. e e-1 e-2 h-16 10?14 16?18 16?18 20-22 xt in , xt out resetb adc8 com7/adc7 com6/adc6 com5/adc5 com4/adc4 p1.0 p1.1?p1.3 p1.4?p1.7 i/o i/o port with bit-programmable pins. configurable to input or push-pull output mode. pull-up resistors can be assigned by software. pins can also be assigned individually as alternative function pins. e-3 e-1 h-14 19?26 23?30 adc3/tbpwm adc2/buz adc1?adc0 com3?com0 p2.0?p2.7 i/o i/o port with bit-programmable pins. configurable to input mode, push-pull output mode. input mode with pull-up resistors can be assigned by software. the port 2 pins have high current drive capability. pins can also be assigned individually as alternative function pins. h-14 30?37 34?41 seg3?seg10 p3.0?p3.2 p3.3 p3.4, p3.6 p3.5 i/o i/o port with bit-programmable pins. configurable to input or push-pull output mode. pull-up resistors can be assigned by software. pins can also be assigned individually as alternative function pins. h-14 h-15 h-17 d-5 d-4 42?44, 1?4 4?10 seg15 seg16/rxd seg17/txd seg18/int0 taout/int1 tack/int2 tacap/int3 p4.0?p4.6 i/o i/o port with bit-programmable pins. configurable to input mode, push-pull output mode. input mode with pull-up resistors can be assigned by software. pins can also be assigned individually as alternative function pins. h-14 27?29 38?41 31?33 42, 1?3 seg0?2 seg11?14 x in , x out i, o system clock input and output pins ? 8,7 14,13 ? test i test signal input pin (for factory use only; must be connected to v ss .) _ 9 15 _ v dd ? power supply input pin ? 5 11 ? v ss ? ground pin ? 6 12 ?
product overview s3 c9484/c9488/f9488 1- 8 table 1-1. pin descriptions of 44-qfp and 42-sdip (continued) pin names pin type pin description circuit type 44 pin no. 42 pin no. shared functions seg0?18 o lcd segment display signal output pins h-14 h-15 h-17 27?44, 1 31?42, 1?7 p4.0?p4.2 p2.0?p2.7 p4.3?p4.6 p3.0 p3.1/rxd p3.2/txd p3.3/int0 com0?7 o lcd common signal output pins h-14 h-16 26?23 18?16 14 30?27 20?22 p1.7?p1.4 p0.4?p0.7 adc0?8 i a/d converter analog input channels e-1 e-3 h-16 22?20 19 18-14 13 20?26 p1.3?p1.2 p1.1/buz p1.0/tbpwm p0.7/com4 p0.6/com5 p0.5/com6 p0.4/com7 p0.3 av ref i a/d converter reference voltage 15 19 rxd i/o serial data rxd pin for receive input and transmit output (mode 0) h-17 43 5 p3.1/seg16 txd o serial data txd pin for transmit output and shift clock output (mode 0) h-17 44 6 p3.2/seg17 int0 int1 int2 int3 i external interrupts. h-15 d-5 d-4 1?4 7?10 p3.3/seg18 p3.4/taout p3.5/tack p3.6/tacap taout o timer/counter(a) overflow output, or timer/counter(a) pwm output d-5 2 8 p3.4/int1 tack i timer/counter(a) external clock input d-4 3 9 p3.5/int2 tacap i timer/counter(a) external capture input d-4 4 10 p3.6/int3 buz o frequency output to buzzer e-3 20 24 p1.1/adc2 tbpwm o timer(b) pwm output e-3 19 23 p1.0/adc3 xt in , xt out i o clock input and output pins for subsystem clock e 10 11 16 17 p0.0 p0.1 resetb i system reset signal input pin b 12 18 p0.2
s3c9484/c9488/f9488 product overview 1- 9 table 1-2. pin descriptions of 32-sop and 32-sdip pin names pin type pin description circuit type 32 pin no. shared functions p0.0, p0.1 p0.2 i/o i/o port with bit-programmable pins. configurable to input or push-pull output mode. pull-up resistors can be assigned by software. pins can also be assigned individually as alternative function pins. e e-2 5?7 xt in , xt out resetb p1.0 p1.1?p1.3 p1.4?p1.7 i/o i/o port with bit-programmable pins. configurable to input or push-pull output mode. pull-up resistors can be assigned by software. pins can also be assigned individually as alternative function pins. e-3 e-1 h-14 9?16 adc3/tbpwm adc2/buz adc1?adc0 com3?com0 p2.0?p2.7 i/o i/o port with bit-programmable pins. configurable to input mode, push-pull output mode, or n-channel open-drain output mode. input mode with pull-up resistors can be assigned by software. the port 2 pins have high current drive capability. pins can also be assigned individually as alternative function pins. h-14 17?24 seg3?seg10 p3.0?p3.2 p3.3 p3.4 p3.5 p3.6 i/o i/o port with bit-programmable pins. configurable to input or push-pull output mode. pull-up resistors can be assigned by software. pins can also be assigned individually as alternative function pins. h-14 h-15 h-17 d-5 d-4 25?31 seg15 seg16/rxd seg17/txd seg18/int0 taout/int1 tack/int2 tacap/int3 x in , x out i, o system clock input and output pins ? 2,3 ? test i test signal input pin (for factory use only; must be connected to v ss .) _ 4 _ v dd ? power supply input pin ? 32 ? v ss ? ground pin ? 1 ?
product overview s3 c9484/c9488/f9488 1- 10 table 1-2. pin descriptions of 32-sop and 32-sdip (continued) pin names pin type pin description circuit type 32 pin no. shared functions seg3?10 seg15?18 o lcd segment display signal output pins h-14 h-15 h-17 17?28 p2.0?p2.7 p3.0 p3.1/rxd p3.2/txd p3.3/int0 com0?3 o lcd common signal output pins h-14 16?13 p1.7?p1.4 adc0?3 i a/d converter analog input channels e-1 e-3 12?9 p1.3?p1.2 p1.1/buz p1.0/tbpwm av ref i a/d converter reference voltage 8 rxd i/o serial data rxd pin for receive input and transmit output (mode 0) h-17 26 p3.1/seg16 txd o serial data txd pin for transmit output and shift clock output (mode 0) h-17 27 p3.2/seg17 int0 int1 int2 int3 i external interrupts. h-15 d-5 d-4 28?31 p3.3/seg18 p3.4/taout p3.5/tack p3.6/tacap taout o timer/counter(a) overflow output, or timer/counter(a) pwm output d-5 29 p3.4/int1 tack i timer/counter(a) external clock input d-4 30 p3.5/int2 tacap i timer/counter(a) external capture input d-4 31 p3.5/int3 buz o frequency output to buzzer e-3 10 p1.1/adc2 tbpwm o timer(b) pwm output e-3 9 p1.0/adc3 xt in , xt out i o clock input and output pins for subsystem clock e 5 6 p0.0 p0.1 resetb i system reset signal input pin b 7 p0.2
s3c9484/c9488/f9488 product overview 1- 11 pin circuits in figure 1-5. pin circuit type b ( reset ) p-channel n-channel v dd out output disable data figure 1-6. pin circuit type c i/o output disable data pin circuit type c pull-up enable v dd figure 1-7. pin circuit type d-2 i/o output disable data pin circuit type c pull-up enable v dd noise filter ext.int input normal v dd figure 1-8. pin circuit type d-4 (p3.5-p3.6)
product overview s3 c9484/c9488/f9488 1- 12 i/o output disable p3.x data pin circuit type c pull-up enable vdd noise filter ext.int normal input vdd m u x alternative output (taout) figure 1-9. pin circuit type d-5 (p3.4) v dd i/o digital input p-ch v dd pull-up enable output disable (input mode) n-ch alternative i/o enable output data xtin,xtout oscillation circuit mux smart option figure 1-10. pin circuit type e (p0.0, p0.1)
s3c9484/c9488/f9488 product overview 1- 13 pull-up enable i/o output disable v dd circuit type c data adc in en to adc data figure 1-11. pin circuit type e-1 (p0.3, p1.2?p1.3) v dd in/out output disable (input mode) data v dd pull-up register (50 k w typical) input data pull-up enable open-drain mux reset mux smart option figure 1-12. pin circuit type e-2 (p0.2)
product overview s3 c9484/c9488/f9488 1- 14 pull-up enable i/o output disable v dd circuit type c data adc in en to adc m u x buzzer output tb underflow carrier on/off (p1.0) port alternative option p1.0 -p1.1 data figure 1-13. pin circuit type e-3 (p1.0- p1.1)
s3c9484/c9488/f9488 product overview 1- 15 out v lc3 seg/com v lc2 v lc4 v lc1 figure 1-14. pin circuit type h (seg/com)
product overview s3 c9484/c9488/f9488 1- 16 out seg v lc4 v lc3 v lc2 output disable v lc1 figure 1-15. pin circuit type h-4 pull-up enable p-ch n-ch v dd i/o output disable data v dd circuit type h open drain en lcd out en seg/com input figure 1-16. pin circuit type h-14 (p1.4-p1.7, p2, p3.0, p4.0-p4.6)
s3c9484/c9488/f9488 product overview 1- 17 pull-up enable p-ch n-ch v dd i/o output disable data v dd circuit type h-4 open drain en lcd out en seg noise filter ext.int normal input figure 1-17. pin circuit type h-15 (p3.3) pull-up enable p-ch n-ch v dd i/o output disable data v dd circuit type h-4 open drain en lcd out en com adc in en normal in adc in figure 1-18. pin circuit type h-16 (p0.4?p0.7)
product overview s3 c9484/c9488/f9488 1- 18 pull-up enable p-ch n-ch v dd i/o output disable data v dd circuit type h-4 open drain en lcd out en seg normal input figure 1-19. pin circuit type h-17 (p3.1-p3.2)
s3c9484/c9488/f9488 address spaces 2- 1 2 address spaces overview the s3c9484/c9488/f9488 microcontroller has two kinds of address space: ? internal program memory (rom) ? internal register file a 13-bit address bus supports program memory operations. a separate 8 -bit register bus carries addresses and data between the cpu and the internal register file. the S3F9488 have 8-kbytes of on-chip program memory, which is configured as the internal rom mode, all of the 8- kbyte internal program memory is used. the s3c9484/c9488/f9488 microcontroller has 208 general-purpose registers in its internal register file. 47 bytes in the register file are mapped for system and peripheral control functions. and 19 bytes in the page1 is mapped for lcd display data area.
address spaces s3c9484/c9488/f9488 2- 2 program memory (rom) program memory (rom) stores program codes or table data. the s3c9484/c9488 has 4k and 8kbytes of internal mask programmable program memory. the program memory address range is therefore 0h?0fffh and 0h-1fffh. the S3F9488 have 8kbytes (locations 0h?1fffh) of internal multi time programmable (mtp) program memory (see figure 2-1) . the first 2-bytes of the rom (0000h?0001h) are interrupt vector address. unused locations (0002h?00ffh except 3ch, 3dh, 3eh, 3fh) can be used as normal program memory. the location 3ch, 3dh, 3eh, and 3fh is used as smart option rom cell. the program reset address in the rom is 0100h. 8,191 1fffh (s3c9488/f9488) 0100h 8kbyte program memory area interrupt vector area 003fh 003ch 0000h (decimal) (hex) program start 0002h 0 smart option rom cell 4kbyte program memory area 4,095 0fffh (s3c9484) 1000h 0200h figure 2-1. program memory address space
s3c9484/c9488/f9488 address spaces 2- 3 smart option smart option is the rom option for starting condition of the chip. the rom addresses used by smart option are from 003ch to 003fh. the default value of rom is ffh. notes: 1. the smart option value of 3dh determine p3.3-p3.6 initial port mode when cpu is reset. the value of smart option is the same as normal setting value. you can refer to user manual chapter "9. i/o port". 2. the unused bits of 3ch, 3eh, 3fh must be logic "1". 3. when lvr is enabled, lvr level must be set to appropriate value, not default value. 4. you must determine p0.0-p0.2 function on smart option. in other words, after reset operation, you cann't change p0.0-p0.2 function. for a example, if you select xtin(p0.0)/xtout(p0.1) function by smart option, you cann't change on normal i/o after reset operation. equally, resetb(p0.2) pin function is the same. rom address: 003dh .7 .6 .5 .4 .3 .2 .1 .0 msb lsb p3conh.7 -.0 the reset value of p3conh (port 3 control register high byte) register is determined by 3dh.7-3dh.0 bits when cpu is reset. rom address: 003eh .7 .6 .5 .4 .3 .2 .1 .0 msb lsb lvr enable or disable bit: 0 = disable 1 = enable lvr level selection bits: 10100 = 2.6 v 01110 = 3.3 v 01011 = 3.9 v not used rom address: 003fh .7 .6 .5 .4 .3 .2 .1 .0 msb lsb not used watchdog timer oscillator select bit: 0 = internal rc oscillator used 1 = basic timer overflow used p0.0/xtin, p0.1/xtout pin function selection bit: 0 = xtin/xtout pin enable 1 = normal i/o pin enable rom address: 003ch .7 .6 .5 .4 .3 .2 .1 .0 msb lsb not used p0.2/resetb pin selection bit: 0 = nomal i/o p0.2 pin enable 1 = resetb pin enable figure 2-2. smart option
address spaces s3c9484/c9488/f9488 2- 4 register architecture the upper 64-bytes of the s3c9484/c9488/f9488's internal register file are addressed as working registers, system control registers and peripheral control registers. the lower 192-bytes of internal register file (00h?bfh) is called the general-purpose register space . 274 registers in this space can be accessed; 208 are available for general-purpose use. and 19 are available for lcd display register. but if lcd driver not used, available for general-purpose use. for many sam88rcri microcontrollers, the addressable area of the internal register file is further expanded by additional register pages at space of the general purpose register (00h?bfh). this register file expansion is not implemented in the s3c9484/c9488/f9488, however. the specific register types and the area (in bytes) that they occupy in the internal register file are summarized in table 2-1. table 2-1. register type summary register type number of bytes system and peripheral registers (page0 & page1) 47 general-purpose registers (including the 16-bit common working register area) 208 lcd display registers (page1) 19 total addressable bytes 274
s3c9484/c9488/f9488 address spaces 2- 5 ffh c0h ~ bfh 00h d0h cfh e0h dfh working registers system control registers peripheral control registers general purpose register file and stack area 22 bytes page 0 00h 15h lcd display registers & peripheral register page 1 192 bytes 64 bytes of common area figure 2-3. internal register file organization
address spaces s3c9484/c9488/f9488 2- 6 common working register area (c0h?cfh) the sam88rcri register architecture provides an efficient method of working register addressing that takes full advantage of shorter instruction formats to reduce execution time. this 16-byte address range is called common area. that is, locations in this area can be used as working registers by operations that address any location on any page in the register file. registers are addressed either as a single 8-bit register or as a paired 16-bit register. in 16-bit register pairs, the address of the first 8-bit register is always an even number and the address of the next register is an odd number. the most significant byte of the 16-bit data is always stored in the even-numbered register; the least significant byte is always stored in the next (+ 1) odd-numbered register. msb rn lsb rn+1 n = even address figure 2-4. 16-bit register pairs
s3c9484/c9488/f9488 address spaces 2- 7 system stack s3f9-series microcontrollers use the system stack for subroutine calls and returns and to store data. the push and pop instructions are used to control system stack operations. the s3c9484/c9488/f9488 architecture supports stack operations in the internal register file. stack operations return addresses for procedure calls and interrupts and data are stored on the stack. the contents of the pc are saved to stack by a call instruction and restored by the ret instruction. when an interrupt occurs, the contents of the pc and the flags registers are pushed to the stack. the iret instruction then pops these values back to their original locations. the stack address always decrements before a push operation and increments after a pop operation. the stack pointer (sp) always points to the stack frame stored on the top of the stack, as shown in figure 2-5. stack contents after a call instruction stack contents after an interrupt top of stack flags pch pcl pcl pch top of stack low address high address figure 2-5. stack operations stack pointer (sp) register location d9h contains the 8-bit stack pointer (sp) that is used for system stack operations. after a reset, the sp value is undetermined. because only internal memory space is implemented in the s3c9484/c9488/f9488, the sp must be initialized to an 8-bit value in the range 00h?0c0h. note in case a stack pointer is initialized to 00h, it is decreased to ffh when stack operation starts. this means that a stack pointer access invalid stack area. we recommend that a stack pointer is initialized to c0h to set upper address of stack to bfh.
address spaces s3c9484/c9488/f9488 2- 8 + programming tip ? standard stack operations using push and pop the following example shows you how to perform stack operations in the internal register file using push and pop instructions: ld sp,#0c0h ; sp ? c0h (normally, the sp is set to c0h by the ; initialization routine) ? ? ? push sym ; stack address 0bfh ? sym push r15 ; stack address 0beh ? r15 push 20h ; stack address 0bdh ? 20h push r3 ; stack address 0bch ? r3 ? ? ? pop r3 ; r3 ? stack address 0bch pop 20h ; 20h ? stack address 0bdh pop r15 ; r15 ? stack address 0beh pop sym ; sym ? stack address 0bfh
s3c9484/c9488/f9488 addressing modes 3- 1 3 addressing modes overview instructions that are stored in program memory are fetched for execution using the program counter. instructions indicate the operation to be performed and the data to be operated on. addressing mode is the method used to determine the location of the data operand. the operands specified in sam88rc instructions may be condition codes, immediate data, or a location in the register file, program memory, or data memory. the s3c-series instruction set supports seven explicit addressing modes. not all of these addressing modes are available for each instruction. the seven addressing modes and their symbols are: ? register (r) ? indirect register (ir) ? indexed (x) ? direct address (da) ? indirect address (ia) ? relative address (ra) ? immediate (im)
addressing modes s3 c9484/c9488/f9488 3- 2 register addressing mode (r) in register addressing mode (r), the operand value is the content of a specified register or register pair (see figure 3-1). working register addressing differs from register addressing in that it uses a register pointer to specify an 8 -byte working register space in the register file and an 8-bit register within that space (see figure 3-2). dst value used in instruction execution opcode operand 8-bit register file address point to one register in register file one-operand instruction (example) sample instruction: dec cntr ; where cntr is the label of an 8-bit register address program memory register file figure 3-1. register addressing dst opcode 4-bit working register point to the working register (1 of 8) two-operand instruction (example) sample instruction: add r1, r2 ; where r1 and r2 are registers in the currently selected working register area. program memory register file src 3 lsbs rp0 or rp1 selected rp points to start of working register block operand msb point to rp0 ot rp1 figure 3-2. working register addressing
s3c9484/c9488/f9488 addressing modes 3- 3 indirect register addressing mode (ir) in indirect register (ir) addressing mode, the content of the specified register or register pair is the address of the operand. depending on the instruction used, the actual address may point to a register in the register file, to program memory (rom), or to an external memory space (see figures 3-3 through 3- 6). you can use any 8-bit register to indirectly address another register. any 16-bit register pair can be used to indirectly address another memory location. dst address of operand used by instruction opcode address 8-bit register file address point to one register in register file one-operand instruction (example) sample instruction: rl @shift ; where shift is the label of an 8-bit register address program memory register file value used in instruction execution operand figure 3-3. indirect register addressing to register file
addressing modes s3 c9484/c9488/f9488 3- 4 indirect register addressing mode (c ontinued ) dst opcode pair points to register pair example instruction references program memory sample instructions: call @rr2 jp @rr2 program memory register file value used in instruction operand register program memory 16-bit address points to program memory figure 3-4. indirect register addressing to program memory
s3c9484/c9488/f9488 addressing modes 3- 5 indirect register addressing mode (c ontinued ) dst opcode address 4-bit working register address point to the working register (1 of 8) sample instruction: or r3, @r6 program memory register file src 3 lsbs value used in instruction operand selected rp points to start fo working register block rp0 or rp1 msb points to rp0 or rp1 ~ ~ ~ ~ figure 3-5. indirect working register addressing to register file
addressing modes s3 c9484/c9488/f9488 3- 6 indirect register addressing mode (c oncluded ) dst opcode 4-bit working register address sample instructions: lcd r5,@rr6 ; program memory access lde r3,@rr14 ; external data memory access lde @rr4, r8 ; external data memory access program memory register file src value used in instruction operand example instruction references either program memory or data memory program memory or data memory next 2-bit point to working register pair (1 of 4) lsb selects register pair 16-bit address points to program memory or data memory rp0 or rp1 msb points to rp0 or rp1 selected rp points to start of working register block figure 3-6. indirect working register addressing to program or data memory
s3c9484/c9488/f9488 addressing modes 3- 7 indexed addressing mode (x) indexed (x) addressing mode adds an offset value to a base address during instruction execution in order to calculate the effective operand address (see figure 3-7). you can use indexed addressing mode to access locations in the internal register file or in external memory. in short offset indexed addressing mode, the 8 -bit displacement is treated as a signed in teger in the range ?128 to +127. this applies to external memory accesses only (see figure 3-8.) for register file addressing, an 8 -bit base address provided by the instruction is added to an 8-bit offset contained in a working register. for external memory accesses, the base address is stored in the working register pair designated in the instruction. the 8-bit or 16-bit offset given in the instruction is then added to that base address (see figure 3-9). the only instruction that supports indexed addressing mode for the internal register file is the load instruction (ld). the ldc and lde instructions support indexed addressing mode for internal program memory and for external data memory, when implemented. dst/src opcode two-operand instruction example point to one of the woking register (1 of 8) sample instruction: ld r0, #base[r1] ; where base is an 8-bit immediate value program memory register file x 3 lsbs value used in instruction operand index base address rp0 or rp1 selected rp points to start of working register block ~ ~ ~ ~ + figure 3-7. indexed addressing to register file
addressing modes s3 c9484/c9488/f9488 3- 8 indexed addressing mode (c ontinued ) register file operand program memory or data memory point to working register pair (1 of 4) lsb selects 16-bit address added to offset rp0 or rp1 msb points to rp0 or rp1 selected rp points to start of working register block dst/src opcode program memory x offset 4-bit working register address sample instructions: ldc r4, #04h[rr2] ; the values in the program address (rr2 + 04h) are loaded into register r4. lde r4,#04h[rr2] ; identical operation to ldc example, except that external program memory is accessed. next 2 bits register pair value used in instruction 8-bits 16-bits 16-bits + ~ ~ figure 3-8. indexed addressing to program or data memory with short offset
s3c9484/c9488/f9488 addressing modes 3- 9 indexed addressing mode (c oncluded ) register file operand program memory or data memory point to working register pair lsb selects 16-bit address added to offset rp0 or rp1 msb points to rp0 or rp1 selected rp points to start of working register block sample instructions: ldc r4, #1000h[rr2] ; the values in the program address (rr2 + 1000h) are loaded into register r4. lde r4,#1000h[rr2] ; identical operation to ldc example, except that external program memory is accessed. next 2 bits register pair value used in instruction 8-bits 16-bits 16-bits dst/src opcode program memory src offset 4-bit working register address offset + ~ ~ figure 3-9. indexed addressing to program or data memory
addressing modes s3 c9484/c9488/f9488 3- 10 direct address mode (da) in direct address (da) mode, the instruction provides the operand's 16-bit memory address. jump (jp) and call (call) instructions use this addressing mode to specify the 16-bit destination address that is loaded into the pc whenever a jp or call instruction is executed. the ldc and lde instructions can use direct address mode to specify the source or destination address for load operations to program memory (ldc) or to external data memory (lde), if implemented. sample instructions: ldc r5,1234h ; the values in the program address (1234h) are loaded into register r5. lde r5,1234h ; identical operation to ldc example, except that external program memory is accessed. dst/src opcode program memory "0" or "1" lower address byte lsb selects program memory or data memory: "0" = program memory "1" = data memory memory address used upper address byte program or data memory figure 3-10. direct addressing for load instructions
s3c9484/c9488/f9488 addressing modes 3- 11 direct address mode (c ontinued ) opcode program memory lower address byte memory address used upper address byte sample instructions: jp c,job1 ; where job1 is a 16-bit immediate address call display ; where display is a 16-bit immediate address next opcode figure 3-11. direct addressing for call and jump instructions
addressing modes s3 c9484/c9488/f9488 3- 12 indirect address mode (ia) in indirect address (ia) mode, the instruction specifies an address located in the lowest 256 bytes of the program memory. the selected pair of memory locations contains the actual address of the next instruction to be executed. only the call instruction can use the indirect address mode. because the indirect address mode assumes that the operand is located in the lowest 256 bytes of program memory, only an 8-bit address is supplied in the instruction; the upper bytes of the destination address are assumed to be all zeros. current instruction program memory locations 0-255 program memory opcode dst lower address byte upper address byte next instruction lsb must be zero sample instruction: call #40h ; the 16-bit value in program memory addresses 40h and 41h is the subroutine start address. figure 3-12. indirect addressing
s3c9484/c9488/f9488 addressing modes 3- 13 relative address mode (ra) in relative address (ra) mode, a twos-complement signed displacement between ? 128 and + 127 is specified in the instruction. the displacement value is then added to the current pc value. the result is the address of the next instruction to be executed. before this addition occurs, the pc contains the address of the instruction immediately following the current instruction. the instructions that support ra addressing is jr. opcode program memory displacement program memory address used sample instructions: jr ult,$+offset ; where offset is a value in the range +127 to -128 next opcode + signed displacement value current instruction current pc value figure 3-13. relative addressing
addressing modes s3 c9484/c9488/f9488 3- 14 immediate mode (im) in immediate (im) addressing mode, the operand value used in the instruction is the value supplied in the operand field itself. immediate addressing mode is useful for loading constant values into registers. (the operand value is in the instruction) opcode sample instruction: ld r0,#0aah program memory operand figure 3-14. immediate addressing
s3c9484/c9488/f9488 control register 4- 1 4 control registers overview control register descriptions are arranged in alphabetical order according to register mnemonic. more detailed information about control registers is presented in the context of the specific peripheral hardware descriptions in part ii of this manual. the locations and read/write characteristics of all mapped registers in the s3c9484/c9488/f9488 register file are listed in table 4-1. the hardware reset value for each mapped register is described in chapter 8, ? reset and power- down." table 4-1. system and peripheral registers register name mnemonic decimal hex r/w lcd control register lcdcon 208 d0h r/w lcd drive voltage control register lcdvol 209 d1h r/w port 0 pull-up resistor control register p0pur 210 d2h r/w port 1 pull-up resistor control register p1pur 211 d3h r/w system clock control register clkcon 212 d4h r/w system flags register flags 213 d5h r/w oscillator control register osccon 214 d6h r/w stop control register stpcon 215 d7h r/w voltage level detector control register vldcon 216 d8h r/w stack pointer register sp 217 d9h r/w location dah - dbh are not mapped basic timer control register btcon 220 dch r/w basic timer counter register btcnt 221 ddh r location deh is not mapped system mode register sym 223 dfh r/w
control registers s 3c9484/c9488/f9488 4- 2 table 4-1. system and peripheral registers (continued) register name mnemonic decimal hex r/w port 0 data register p0 224 e0h r/w port 1 data register p1 225 e1h r/w port 2 data register p2 226 e2h r/w port 3 data register p3 227 e3h r/w port 4 data register p4 228 e4h r/w watchdog timer control register wdtcon 229 e5h r/w port 0 control high register p0conh 230 e6h r/w port 0 control low register p0conl 231 e7h r/w port 1 control high register p1conh 232 e8h r/w port 1 control low register p1conl 233 e9h r/w port 2 control high register p2conh 234 eah r/w port 2 control low register p2conl 235 ebh r/w port 3 control high register p3conh 236 ech r/w port 3 control low register p3conl 237 edh r/w port 3 interrupt control register p3int 238 eeh r/w port 3 interrupt pending register p3pnd 239 efh r/w port 4 control high register p4conh 240 f0h r/w port 4 control low register p4conl 241 f1h r/w timer a/timer b interrupt pending register tintpnd 242 f2h rw timer a control register tacon 243 f3h r/w timer a counter register tacnt 244 f4h r timer a data register tadata 245 f5h r/w timer b data register(high byte) tbdatah 246 f6h r/w timer b data register(low byte) tbdatal 247 f7h r/w timer b control register tbcon 248 f8h r/w watch timer control register wtcon 249 f9h r/w a/d converter data register(high byte) addatah 250 fah r a/d converter data register(low byte) addatal 251 fbh r a/d converter control register adcon 252 fch r/w uart control register uartcon 253 fdh r/w uart pending register uartpnd 254 feh r/w uart data register udata 255 ffh r/w
s3c9484/c9488/f9488 control register 4- 3 table 4-2. lcd display register and peripheral registers (page 1) register name mnemonic decimal hex r/w lcd display ram - 0 00h r/w lcd display ram - 1 01h r/w lcd display ram - 2 02h r/w lcd display ram - 3 03h r/w lcd display ram - 4 04h r/w lcd display ram - 5 05h r/w lcd display ram - 6 06h r/w lcd display ram - 7 07h r/w lcd display ram - 8 08h r/w lcd display ram - 9 09h r/w lcd display ram - 10 0ah r/w lcd display ram - 11 0bh r/w lcd display ram - 12 0ch r/w lcd display ram - 13 0dh r/w lcd display ram - 14 0eh r/w lcd display ram - 15 0fh r/w lcd display ram - 16 10h r/w lcd display ram - 17 11h r/w lcd display ram - 18 12h r/w location 13h is not mapped uart baud rate data register (high byte) brdatah 20 14h r/w uart baud rate data register (low byte) brdatal 21 15h r/w note: when you use the sk-1000(sk-8xx) mds , the brdatah/brdatal of mnemonic isn?t showed on the system reg ister window of mds application program, because brdatah/brdatal is located on the general register page1.
control registers s 3c9484/c9488/f9488 4- 4 flags - system flags register .7 carry flag (c) .6 zero flag (z) .5 bit identifier reset value read/write r = read-only w = write-only r/w = read/write '-' = not used reset value notation: '-' = not used 'x' = undetermined value '0' = logic zero '1' = logic one bit number(s) that is/are appended to the register name for bit addressing name of individual bit or related bits register name register id sign flag (s) 0 operation does not generate a carry or borrow condition 0 operation generates carry-out or borrow into high-order bit 7 0 operation result is a non-zero value 0 operation result is zero 0 operation generates positive number (msb = "0") 0 operation generates negative number (msb = "1") description of the effect of specific bit settings d5h register address (hexadecimal) .7 .6 .5 x r/w .4 .3 .2 bit number: msb = bit 7 lsb = bit 0 .1 .0 x r/w x r/w x r/w figure 4-1. register description format
s3c9484/c9488/f9488 control register 4- 5 adcon ? a/d converter control register fch bit identifier .7 .6 .5 .4 .3 .2 .1 .0 reset value 0 0 0 0 0 0 0 0 read/write r/w r/w r/w r/w r/w r/w r/w r/w .7-.4 a/d input pin selection bits 0 0 0 0 adc0 0 0 0 1 adc1 0 0 1 0 adc2 0 0 1 1 adc3 0 1 0 0 adc4 0 1 0 1 adc5 0 1 1 0 adc6 0 1 1 1 adc7 1 0 0 0 adc8 other value connected with gnd internally .3 end-of-conversion (eoc) status bit 0 a/d conversion is in progress 1 a/d conversion complete .2-.1 clock source selection bits 0 0 fxx/16 (fosc 8mhz) 0 1 fxx/8 (fosc 8mhz) 1 0 fxx/4 (fosc 8mhz) 1 1 fxx (fosc 2.5mhz) .0 a/d conversion start bit 0 disable operation 1 start operation note : maximum adc clock input = 4mhz.
control registers s 3c9484/c9488/f9488 4- 6 btcon ? basic timer control register dch bit identifier .7 .6 .5 .4 .3 .2 .1 .0 reset value ? ? ? ? 0 0 0 0 read/write ? ? ? ? r/w r/w r/w r/w .7-.4 not used for the s3c9484/c9488/f9488 .3-.2 basic timer input clock selection bits 0 0 fxx/4096 (3) 0 1 fxx/1024 1 0 fxx/128 1 1 not used .1 basic timer counter clear bit (1) 0 no effect 1 clear the basic timer counter value .0 clock frequency divider clear bit for basic timer (2) 0 no effect 1 clear both clock frequency dividers notes: 1. when you write a ?1? to btcon.1, the basic timer counter value is cleared to "00h". immediate ly following the write operation, the btcon.1 value is automatically cleared to ?0?. 2. when you write a "1" to btcon.0, the corresponding frequency divider is cleared to "00h". immediately following the write operation, the btcon.0 value is automatically cleared to "0". 3. the fxx is selected clock for system (main osc. or sub osc).
s3c9484/c9488/f9488 control register 4- 7 clkcon ? system clock control register d4h bit identifier .7 .6 .5 .4 .3 .2 .1 .0 reset value 0 ? ? 0 0 ? ? ? read/write r/w ? ? r/w r/w ? ? ? .7 oscillator irq wake-up function enable bit 0 enable irq for main system oscillator wake-up function 1 disable irq for main system oscillator wake-up function .6-.5 not used for the s3c9484/c9488/f9488 .4-.3 cpu clock (system clock) selection bits (note) 0 0 fxx/16 0 1 fxx/8 1 0 fxx/2 1 1 fxx/1 (non-divided) .2-.0 not used for the s3c9484/c9488/f9488 note: after a reset, the slowest clock (divided by 16) is selected as the system clock. to select faster clock speeds, load the appropriate values to clkcon.3 and clkcon.4.
control registers s 3c9484/c9488/f9488 4- 8 flags ? system flags register d5h bit identifier .7 .6 .5 .4 .3 .2 .1 .0 reset /value x x x x ? ? ? ? read/write r/w r/w r/w r/w ? ? ? ? .7 carry flag (c) 0 operation does not generate a carry or borrow condition 1 operation generates a carry-out or borrow into high-order bit 7 .6 zero flag (z) 0 operation result is a non-zero value 1 operation result is zero .5 sign flag (s) 0 operation generates a positive number (msb = "0") 1 operation generates a negative number (msb = "1") .4 overflow flag (v) 0 operation result is + 127 or _ ? 128 1 operation result is > + 127 or < ? 128 .3?.0 not used for the s3c9484/c9488/f9488
s3c9484/c9488/f9488 control register 4- 9 lcdcon ? lcd control register d0h bit identifier .7 .6 .5 .4 .3 .2 .1 .0 reset value 0 ? 0 0 0 0 0 0 read/write r/w ? r/w r/w r/w r/w r/w r/w .7 lcd module enable/disable bit 0 disable lcd module 1 enable lcd module .6 not used for the s3c9484/c9488/f9488 .5-.4 lcd duty selection bit 0 0 1/8 duty , 1/4 bias 0 1 1/4 duty , 1/3 bias 1 x static .3-.2 lcd dot on/off control bits 0 0 off signal 0 1 on signal 1 x normal display .1-.0 lcd clock signal selection bits 0 0 fw/2 7 0 1 fw/2 6 1 0 fw/2 5 1 1 fw/2 4
control registers s 3c9484/c9488/f9488 4- 10 lcdvol ? lcd voltage control register d1h bit identifier .7 .6 .5 .4 .3 .2 .1 .0 reset value 0 ? ? ? 0 0 0 0 read/write r/w ? ? ? r/w r/w r/w r/w .7 lcd contrast control enable/disable bit 0 disable lcd contrast module 1 enable lcd contrast module .6-.4 not used for the s3c9484/c9488/f9488 .3-.0 lcd segment/port output selection bits: 0 0 0 0 1/16 step (the dimmest level) 0 0 0 1 2/16 step 0 0 1 0 3/16 step 0 0 1 1 4/16 step 0 1 0 0 5/16 step 0 1 0 1 6/16 step 0 1 1 0 7/16 step 0 1 1 1 8/16 step 1 0 0 0 9/16 step 1 0 0 1 10/16 step 1 0 1 0 11/16 step 1 0 1 1 12/16 step 1 1 0 0 13/16 step 1 1 0 1 14/16 step 1 1 1 0 15/16 step 1 1 1 1 16/16 step
s3c9484/c9488/f9488 control register 4- 11 osccon ? oscillator control register d6h bit identifier .7 .6 .5 .4 .3 .2 .1 .0 reset value ? ? ? ? 0 0 ? 0 read/write ? ? ? ? r/w r/w ? r/w .7-.4 not used for the s3c9484/c9488/f9488 .3 main system oscillator control bit 0 main system oscillator run 1 main system oscillator stop .2 sub system oscillator control bit 0 sub system oscillator run 1 sub system oscillator stop .1 not used for the s3c9484/c9488/f9488 .0 system clock selection bit 0 main oscillator select 1 subsystem oscillator select
control registers s 3c9484/c9488/f9488 4- 12 p0conh ? port 0 control register (high byte) e6h bit identifier .7 .6 .5 .4 .3 .2 .1 .0 reset value 0 0 0 0 0 0 0 0 read/write r/w r/w r/w r/w r/w r/w r/w r/w .7-.6 p0.7/com4/adc4 0 0 input mode 0 1 alternative function; adc4 input 1 0 push-pull output 1 1 alternative function; lcd com4 signal output .5-.4 p0.6/com5/adc5 0 0 input mode 0 1 alternative function; adc5 input 1 0 push-pull output 1 1 alternative function; lcd com5 signal output .3?.2 p0.5/ com6/adc6 0 0 input mode 0 1 alternative function; adc6 input 1 0 push-pull output 1 1 alternative function; lcd com6 signal output .1?.0 p0.4/ com7/adc7 0 0 input mode 0 1 alternative function; adc7 input 1 0 push-pull output 1 1 alternative function; lcd com7 signal output note: when users use port 0, users must be care of the pull-up resistance status.
s3c9484/c9488/f9488 control register 4- 13 p0conl ? port 0 control register (low byte) e7h bit identifier .7 .6 .5 .4 .3 .2 .1 .0 reset value 0 0 0 0 0 0 0 0 read/write r/w r/w r/w r/w r/w r/w r/w r/w .7?.6 p0.3/adc8 0 x input mode 1 0 push-pull output 1 x alternative function; adc8 input .5?.4 p0.2 0 x input mode 1 x push-pull output .3?.2 p0.1 0 x input mode 1 x push-pull output .1?.0 p0.0 0 x input mode 1 x push-pull output notes : 1. if you selected the xtin/xtout function at smart option, no relations to p0conl.3 -.0 bit value. but if you selected the normal i/o function at smart option, the reset value of p0conl.3 -.0 bits are ?0000?. 2. when users use port 0, users must be care of the pull-up resistan ce status.
control registers s 3c9484/c9488/f9488 4- 14 p0pur ? port 0 pull-up resistor control register d2h bit identifier .7 .6 .5 .4 .3 .2 .1 .0 reset value 1 1 1 1 1 1 1 1 read/write r/w r/w r/w r/w r/w r/w r/w r/w .7 p0.7 pull-up resistor enable/disable 0 pull-up resistor disable 1 pull-up resistor enable .6 p0.6 pull-up resistor enable/disable 0 pull-up resistor disable 1 pull-up resistor enable .5 p0.5 pull-up resistor enable/disable 0 pull-up resistor disable 1 pull-up resistor enable .4 p0.4 pull-up resistor enable/disable 0 pull-up resistor disable 1 pull-up resistor enable .3 p0.3 pull-up resistor enable/disable 0 pull-up resistor disable 1 pull-up resistor enable .2 p0.2 pull-up resistor enable/disable 0 pull-up resistor disable 1 pull-up resistor enable .1 p0.1 pull-up resistor enable/disable 0 pull-up resistor disable 1 pull-up resistor enable .0 p0.0 pull-up resistor enable/disable 0 pull-up resistor disable 1 pull-up resistor enable
s3c9484/c9488/f9488 control register 4- 15 p1conh ? port 1 control register (high byte) e8h bit identifier .7 .6 .5 .4 .3 .2 .1 .0 reset value 0 0 0 0 0 0 0 0 read/write r/w r/w r/w r/w r/w r/w r/w r/w .7-.6 p1.7/com0 0 x input mode 1 0 push-pull output 1 1 alternative function; lcd com0 signal output .5-.4 p1.6/com1 0 x input mode 1 0 push-pull output 1 1 alternative function; lcd com1 signal output .3-.2 p1.5/com2 0 x input mode 1 0 push-pull output 1 1 alternative function; lcd com2 signal output .1-.0 p1.4/com3 0 x input mode 1 0 push-pull output 1 1 alternative function; lcd com3 signal output note: when users use port 1, users must be care of the pull-up resistance status.
control registers s 3c9484/c9488/f9488 4- 16 p1conl ? port 1 control register (low byte) e9h bit identifier .7 .6 .5 .4 .3 .2 .1 .0 reset value 0 0 0 0 0 0 0 0 read/write r/w r/w r/w r/w r/w r/w r/w r/w .7-.6 p1.3/adc0 0 x input mode 1 0 push-pull output 1 1 alternative function; adc0 input .5-.4 p1.2/adc1 0 x input mode 1 0 push-pull output 1 1 alternative function; adc1 input .3-.2 p1.1/adc2/buz 0 0 input mode 0 1 alternative function; buz output 1 0 push-pull output 1 1 alternative function; adc2 input .1-.0 p1.0/adc3/tbpwm 0 0 input mode 0 1 alternative function; tbpwm output 1 0 push-pull output 1 1 alternative function; adc3 input note: when users use port 1, users must be care of the pull-up resistance status.
s3c9484/c9488/f9488 control register 4- 17 p1pur ? port 1 pull-up resistor control register d3h bit identifier .7 .6 .5 .4 .3 .2 .1 .0 reset value 1 1 1 1 1 1 1 1 read/write r/w r/w r/w r/w r/w r/w r/w r/w .7 p1.7 pull-up resistor enable/disable 0 pull-up resistor disable 1 pull-up resistor enable .6 p1.6 pull-up resistor enable/disable 0 pull-up resistor disable 1 pull-up resistor enable .5 p1.5 pull-up resistor enable/disable 0 pull-up resistor disable 1 pull-up resistor enable .4 p1.4 pull-up resistor enable/disable 0 pull-up resistor disable 1 pull-up resistor enable .3 p1.3 pull-up resistor enable/disable 0 pull-up resistor disable 1 pull-up resistor enable .2 p1.2 pull-up resistor enable/disable 0 pull-up resistor disable 1 pull-up resistor enable .1 p1.1 pull-up resistor enable/disable 0 pull-up resistor disable 1 pull-up resistor enable .0 p1.0 pull-up resistor enable/disable 0 pull-up resistor disable 1 pull-up resistor enable
control registers s 3c9484/c9488/f9488 4- 18 p2conh ? port 2 control register (high byte) eah bit identifier .7 .6 .5 .4 .3 .2 .1 .0 reset value 0 0 0 0 0 0 0 0 read/write r/w r/w r/w r/w r/w r/w r/w r/w .7?.6 p2.7/seg10 0 0 input mode with pull-up 0 1 input mode 1 0 push-pull output 1 1 alternative function; lcd seg10 signal output .5-.4 p2.6/seg9 0 0 input mode with pull-up 0 1 input mode 1 0 push-pull output 1 1 alternative function; lcd seg9 signal output .3?.2 p2.5/seg8 0 0 input mode with pull-up 0 1 input mode 1 0 push-pull output 1 1 alternative function; lcd seg8 signal output .1?.0 p2.4/seg7 0 0 input mode with pull-up 0 1 input mode 1 0 push-pull output 1 1 alternative function; lcd seg7 signal output
s3c9484/c9488/f9488 control register 4- 19 p2conl ? port 2 control register (low byte) ebh bit identifier .7 .6 .5 .4 .3 .2 .1 .0 reset value 0 0 0 0 0 0 0 0 read/write r/w r/w r/w r/w r/w r/w r/w r/w .7-.6 p2.3/seg6 0 0 input mode with pull-up 0 1 input mode 1 0 push-pull output 1 1 alternative function; lcd seg6 signal output .5-.4 p2.2/seg5 0 0 input mode with pull-up 0 1 input mode 1 0 push-pull output 1 1 alternative function; lcd seg5 signal output .3-.2 p2.1/seg4 0 0 input mode with pull-up 0 1 input mode 1 0 push-pull output 1 1 alternative function; lcd seg4 signal output .1-.0 p2.0/seg3 0 0 input mode with pull-up 0 1 input mode 1 0 push-pull output 1 1 alternative function; lcd seg3 signal output
control registers s 3c9484/c9488/f9488 4- 20 p3conh ? port 3 control register (high byte) ech bit identifier .7 .6 .5 .4 .3 .2 .1 .0 reset value s s s s s s s s read/write r/w r/w r/w r/w r/w r/w r/w r/w .7?.6 p3.6/tacap/int3 0 0 input mode with pull-up; interrupt(int3) input; tacap 0 1 input mode; interrupt(int3) input; tacap 1 x push-pull output .5?.4 p3.5/tack/int2 0 0 input mode with pull-up; interrupt(int2) input; tack 0 1 input mode; interrupt(int2) input; tack 1 x push-pull output .3?.2 p3.4/taout(tapwm)/int1 0 0 input mode with pull-up; interrupt(int1) input 0 1 input mode; interrupt(int1) input 1 0 push-pull output 1 1 alternative function; taout(tapwm) .1?.0 p3.3/seg18/int0 0 0 input mode with pull-up; interrupt(int0) input 0 1 input mode; interrupt(int0) input 1 0 push-pull output 1 1 alternative function; lcd seg18 signal output note: ?s? of reset value mean that reset value is set by smart option.
s3c9484/c9488/f9488 control register 4- 21 p3conl ? port 3 control register (low byte) edh bit identifier .7 .6 .5 .4 .3 .2 .1 .0 reset value 0 0 0 0 0 0 0 0 read/write r/w r/w r/w r/w r/w r/w r/w r/w .7-.5 p3.2/seg17/txd 0 0 0 input mode with pull-up 0 0 1 input mode 0 1 0 push-pull output 0 1 1 alternative function; txd output 1 x x alternative function; lcd seg17 signal output .4-.2 p3.1/seg16/rxd 0 0 0 input mode with pull-up; rxd input 0 0 1 input mode; rxd input 0 1 0 push-pull output 0 1 1 alternative function; rxd output 1 x x alternative function; lcd seg16 signal output .1-.0 p3.0/ seg15 0 0 input mode with pull-up 0 1 input mode 1 0 push-pull output 1 1 alternative function; lcd seg15 signal output
control registers s 3c9484/c9488/f9488 4- 22 p3int ? port 3 interrupt control register eeh bit identifier .7 .6 .5 .4 .3 .2 .1 .0 reset value 0 0 0 0 0 0 0 0 read/write r/w r/w r/w r/w r/w r/w r/w r/w .7-.6 p3.6/ int3 interrupt enable/disable selection bits 0 x interrupt disable 1 0 interrupt enable; falling edge 1 1 interrupt enable; rising edge .5-.4 p3.5/ int2 interrupt enable/disable selection bits 0 x interrupt disable 1 0 interrupt enable; falling edge 1 1 interrupt enable; rising edge .3-.2 p3.4/ int1 interrupt enable/disable selection bits 0 x interrupt disable 1 0 interrupt enable; falling edge 1 1 interrupt enable; rising edge .1-.0 p3.3/int0 interrupt enable/disable selection bits 0 x interrupt disable 1 0 interrupt enable; falling edge 1 1 interrupt enable; rising edge
s3c9484/c9488/f9488 control register 4- 23 p3pnd ? port 3 interrupt pending register efh bit identifier .7 .6 .5 .4 .3 .2 .1 .0 reset value ? ? ? ? 0 0 0 0 read/write ? ? ? ? r/w r/w r/w r/w .7-.4 not used for the s3c9484/c9488/f9488 .3 p3.6/int3 interrupt pending bit 0 interrupt request is not pending, pending bit clear when write 0 1 interrupt request is pending .2 p3.5/int2 interrupt pending bit 0 interrupt request is not pending, pending bit clear when write 0 1 interrupt request is pending .1 p3.4/int1 interrupt pending bit 0 interrupt request is not pending, pending bit clear when write 0 1 interrupt request is pending .0 p3.3/int0 interrupt pending bit 0 interrupt request is not pending, pending bit clear when write 0 1 interrupt request is pending
control registers s 3c9484/c9488/f9488 4- 24 p4conh ? port 4 control register (high byte) f0h bit identifier .7 .6 .5 .4 .3 .2 .1 .0 reset value ? ? 0 0 0 0 0 0 read/write ? ? r/w r/w r/w r/w r/w r/w .7?.6 not used for the s3c9484/c9488/f9488 .5-.4 p4.6/seg14 0 0 input mode with pull-up 0 1 input mode 1 0 push-pull output 1 1 alternative function; lcd seg14 signal output .3?.2 p4.5/seg13 0 0 input mode with pull-up 0 1 input mode 1 0 push-pull output 1 1 alternative function; lcd seg13 signal output .1?.0 p4.4/seg12 0 0 input mode with pull-up 0 1 input mode 1 0 push-pull output 1 1 alternative function; lcd seg12 signal output
s3c9484/c9488/f9488 control register 4- 25 p4conl ? port 4 control register (low byte) f1h bit identifier .7 .6 .5 .4 .3 .2 .1 .0 reset value 0 0 0 0 0 0 0 0 read/write r/w r/w r/w r/w r/w r/w r/w r/w .7-.6 p4.3/seg11 0 0 input mode with pull-up 0 1 input mode 1 0 push-pull output 1 1 alternative function; lcd seg11 signal output .5-.4 p4.2/seg2 0 0 input mode with pull-up 0 1 input mode 1 0 push-pull output 1 1 alternative function; lcd seg2 signal output .3-.2 p4.1/seg1 0 0 input mode with pull-up 0 1 input mode 1 0 push-pull output 1 1 alternative function; lcd seg1signal output .1-.0 p4.0/seg0 0 0 input mode with pull-up 0 1 input mode 1 0 push-pull output 1 1 alternative function; lcd seg0 signal output
control registers s 3c9484/c9488/f9488 4- 26 sp ? stack pointer d9h bit identifier .7 .6 .5 .4 .3 .2 .1 .0 reset value x x x x x x x x read/write r/w r/w r/w r/w r/w r/w r/w r/w .7?.0 stack pointer address the stack pointer value is 8-bit stack pointer address (sp7?sp0). the sp value is undefined following a reset. stpcon ? stop control register d7h bit identifier .7 .6 .5 .4 .3 .2 .1 .0 reset value 0 0 0 0 0 0 0 0 read/write r/w r/w r/w r/w r/w r/w r/w r/w .7?.0 stop control bits 1 0 1 0 0 1 0 1 enable stop instruction other values disable stop instruction note: before executing the stop instruction, you must set this stpcon register as ?10100101b?. otherwise the stop instruction will not be executed.
s3c9484/c9488/f9488 control register 4- 27 sym ? system mode register dfh bit identifier .7 .6 .5 .4 .3 .2 .1 .0 reset value ? ? ? ? 0 0 0 0 read/write ? ? ? ? r/w r/w r/w r/w .7?.4 not used for s3c9484/c9488/f9488 .3 global interrupt enable bit 0 disable all interrupts 1 enable all interrupt .2?.0 page select bits 0 0 0 page 0 0 0 1 page 1 0 1 0 page 2 (not used for s3c9484/c9488/f9488 ) 0 1 1 page 3 (not used for s3c9484/c9488/f9488 ) 1 0 0 page 4 (not used for s3c9484/c9488/f9488 ) 1 0 1 page 5 (not used for s3c9484/c9488/f9488 ) 1 1 0 page 6 (not used for s3c9484/c9488/f9488 ) 1 1 1 page 7 (not used for s3c9484/c9488/f9488 ) note: following a reset, you must enable global interrupt processing by executing an ei instruction (not by writing a "1" to sym.3).
control registers s 3c9484/c9488/f9488 4- 28 tacon ? timer a control register f3h bit identifier .7 .6 .5 .4 .3 .2 .1 .0 reset value 0 0 0 0 0 0 0 0 read/write r/w r/w r/w r/w r/w r/w r/w r/w .7-.6 timer a input clock selection bits 0 0 fxx/1024 0 1 fxx/256 1 0 fxx/64 1 1 external clock (tack) .5-.4 timer a operating mode selection bits 0 0 internal mode (taout mode) 0 1 capture mode (capture on rising edge, counter running, ovf can occur) 1 0 capture mode (capture on falling edge, counter running, ovf can occur) 1 1 pwm mode (ovf interrupt can occur) .3 timer a counter clear bit 0 no effect 1 clear the timer a counter (after clearing, return to zero) .2 timer a overflow interrupt enable bit 0 disable interrupt 1 enable interrupt .1 timer a match/capture interrupt enable bit 0 disable interrupt 1 enable interrupt .0 timer a start/stop bit 0 stop timer a 1 start timer a
s3c9484/c9488/f9488 control register 4- 29 tbcon ? timer b control register f8h bit identifier .7 .6 .5 .4 .3 .2 .1 .0 reset value 0 0 0 0 0 0 0 0 read/write r/w r/w r/w r/w r/w r/w r/w r/w .7?.6 timer b input clock selection bits 0 0 fxx 0 1 fxx/2 1 0 fxx/4 1 1 fxx/8 .5?.4 timer b interrupt time selection bits 0 0 elapsed time for low data value 0 1 elapsed time for high data value 1 0 elapsed time for low and high data values 1 1 invalid setting .3 timer b underflow interrupt enable bit 0 disable interrupt 1 enable interrupt .2 timer b start/stop bit 0 stop timer b 1 start timer b .1 timer b mode selection bit 0 one-shot mode 1 repeating mode .0 timer b output flip-flop control bit 0 t-ff is low 1 t-ff is high note: fxx is selected clock for system.
control registers s 3c9484/c9488/f9488 4- 30 tintpnd ? timer a,b interrupt pending register f2h bit identifier .7 .6 .5 .4 .3 .2 .1 .0 reset value ? ? ? ? ? 0 0 0 read/write ? ? ? ? ? r/w r/w r/w .7-.3 not used for the s3c9484/c9488/f9488 .2 timer b underflow interrupt pending bit 0 no interrupt pending 0 clear pending bit when write 1 interrupt pending .1 timer a overflow interrupt pending bit 0 no interrupt pending 0 clear pending bit when write 1 interrupt pending .0 timer a match/capture interrupt pending bit 0 no interrupt pending 0 clear pending bit when write 1 interrupt pending
s3c9484/c9488/f9488 control register 4- 31 uartcon ? uart control register fdh bit identifier .7 .6 .5 .4 .3 .2 .1 .0 reset value 0 0 0 0 0 0 0 0 read/write r/w r/w r/w r/w r/w r/w r/w r/w .7?.6 operating mode and baud rate selection bits 0 0 mode 0: shift register [fxx/(16 (16bit brdata + 1))] 0 1 mode 1: 8-bit uart [fxx/(16 (16bit brdata + 1))] 1 x mode 2: 9-bit uart [fxx/(16 (16bit brdata + 1))] .5 multiprocessor communication (1) enable bit (for modes 2 only) 0 disable 1 enable .4 serial data receive enable bit 0 disable 1 enable .3 if parity disable mode (pen = 0), location of the 9 th data bit to be transmitted in uart mode 2 ("0" or "1"). if parity enable mode (pen = 1), even/odd parity selection bit for transmit data in uart mode 2. 0: even parity bit generation for transmit data 1: odd parity bit generation for transmit data
control registers s 3c9484/c9488/f9488 4- 32 uartcon ? uart control register (continued) fdh bit identifier .7 .6 .5 .4 .3 .2 .1 .0 reset value 0 0 0 0 0 0 0 0 read/write r/w r/w r/w r/w r/w r/w r/w r/w .2 if parity disable (pen = 0), location of the 9 th data bit that was received in uart mode 2 ("0" or "1"). if parity enable mode (pen = 1), even/odd parity selection bit for receive data in uart mode 2. 0: even parity check for the received data 1: odd parity check for the received data a result of parity error will be saved in rpe bit of the uartpnd register after parity checking of the received data. .1 receive interrupt enable bit 0 disable receive interrupt 1 enable receive interrupt .0 transmit interrupt enable bit 0 disable transmit interrupt 1 enable transmit interrupt notes: 1. in mode 2, if the mce (uartcon.5) bit is set to "1", the receive interrupt will not be activated if the received 9 th data bit is "0". in mode 1, if mce = "1?, the receive interrupt will not be activated if a valid stop bit was not received. in mode 0, the mce (uartcon.5) bit should be "0". 2. the descriptions for 8-bit and 9-bit uart mode don?t include start and stop bits for serial data receive and transmit. 3. parity enable bits, pen, are located in the uartpnd register at address feh. 4. parity enable and parity error check can be available in 9-bit uart mode (mode 2) only.
s3c9484/c9488/f9488 control register 4- 33 uartpnd ? uart pending and parity control feh bit identifier .7 .6 .5 .4 .3 .2 .1 .0 reset value ? ? 0 0 ? ? 0 0 read/write ? ? r/w r/w ? ? r/w r/w .7-.6 not used for the s3c9484/c9488/f9488 .5 uart parity enable/disable (pen) 0 disable 1 enable .4 uart receive parity error (rpe) 0 no error 1 parity error .3-.2 not used for the s3c9484/c9488/f9488 .1 uart receive interrupt pending flag 0 not pending 0 clear pending bit (when write) 1 interrupt pending .0 uart transmit interrupt pending flag 0 not pending 0 clear pending bit (when write) 1 interrupt pending notes: 1. in order to clear a data transmit or receive interrupt pending flag, you must write a "0" to the appropriate pending bit. 2. to avoid programming errors, we recommend using load instruction (except for l db), when manipulating uartpnd values. 3. parity enable and parity error check can be available in 9-bit uart mode (mode 2) only. 4. parity error bit (rpe) will be refreshed whenever 8th receive data bit has been shifted.
control registers s 3c9484/c9488/f9488 4- 34 vldcon ? voltage level detector control register d8h bit identifier .7 .6 .5 .4 .3 .2 .1 .0 reset value ? 0 1 0 1 1 0 0 read/write ? r r/w r/w r/w r/w r/w r/w .7 not used for the s3c9484/c9488/f9488 .6 v ld level set bit 0 v dd is higher than reference voltage 1 v dd is lower than reference voltage .5-.1 reference voltage selection bits 10110 v vld = 2.4 v 10011 v vld = 2.7 v 01110 v vld = 3.3 v 01011 v vld = 3.9 v other values don?t care .0 v ld operation enable bit 0 operation off 1 operation on
s3c9484/c9488/f9488 control register 4- 35 wdtcon ? watchdog timer control register e5h bit identifier .7 .6 .5 .4 .3 .2 .1 .0 reset value 0 0 0 0 0 0 0 0 read/write r/w r/w r/w r/w r/w r/w r/w r/w .7-.4 watchdog timer function enable bits (for system reset) 1 0 1 0 disable watchdog timer function other values enable watchdog timer function .3-.0 watchdog timer counter clear bits 1 0 1 0 clear watchdog timer counter other values don?t care
control registers s 3c9484/c9488/f9488 4- 36 wtcon ? watch timer control register f9h bit identifier .7 .6 .5 .4 .3 .2 .1 .0 reset value 0 0 0 0 0 0 0 0 read/write r/w r/w r/w r/w r/w r/w r/w r/w .7 watch timer clock selection bit 0 main system clock divided by 2 7 (fxx/128) 1 sub system clock (fxt) .6 watch timer interrupt enable bit 0 disable watch timer interrupt 1 enable watch timer interrupt .5?.4 buzzer signal selection bits 0 0 0.5 khz buzzer (buz) signal output 0 1 1 khz buzzer (buz) signal output 1 0 2 khz buzzer (buz) signal output 1 1 4 khz buzzer (buz) signal output .3?.2 watch timer speed selection bits 0 0 1.0 s interval 0 1 0.5 s interval 1 0 0.25 s interval 1 1 3.91 ms interval .1 watch timer enable bit 0 disable watch timer; clear frequency dividing circuits 1 enable watch timer .0 watch timer interrupt pending bit 0 interrupt is not pending, clear pending bit when write 1 interrupt is pending
s3c9484/c9488/f9488 interrupt structur e 5- 1 5 interrupt structure overview the sam88rcri interrupt structure has two basic components: a vector, and sources. the number of interrupt sources can be serviced through an interrupt vector which is assigned in rom address 0000h. vector sources 0000h 0001h notes: 1. the sam88rcri interrupt has only one vector address (0000h-0001h). 2. the numbern of sn value is expandable. s1 s2 s3 sn figure 5-1. s3c9-series interrupt type interrupt processing control points interrupt processing can be controlled in two ways: either globally or specific interrupt level and source. the system-level control points in the interrupt structure are therefore: ? global interrupt enable and disable (by ei and di instructions) ? interrupt source enable and disabl e settings in the corresponding peripheral control register(s)
interrupt structure s3c9484/c9488/f9488 5- 2 enable/disable interrupt instructions (ei, di) the system mode register, sym (dfh), is used to enable and disable interrupt processing. sym.3 is the enable and disable bit for global interrupt processing respectively, by modifying sym.3. an enable interrupt (ei) instruction must be included in the initialization routine that follows a reset operation in order to enable interrupt processing. although you can manipulate sym.3 directly to enable and disable interrupts during normal operation, we recommend that you use the ei and di instructions for this purpose. interrupt pending function types when the interrupt service routine has executed, the application program's service routine must clear the appropriate pending bit before the return from interrupt subroutine (iret) occurs. interrupt priority because there is not a interrupt priority register in sam88rcri, the order of service is determined by a sequence of source which is executed in interrupt service routine. interrupt pending register global interrupt control (ei, di instruction) vector interrupt cycle interrpt priority is determind by software polling method "ei" instruction execution reset source interrupts source interrupt enable s r q figure 5-2. interrupt function diagram
s3c9484/c9488/f9488 interrupt structur e 5- 3 interrupt source service sequence the interrupt request polling and servicing sequence is as follows: 1. a source generates an interrupt request by setting the interrupt request pending bit to "1". 2. the cpu generates an interrupt ac knowledge signal. 3. the service routine starts and the source's pending flag is cleared to "0" by software. 4. interrupt priority must be determined by software polling method. interrupt service routines before an interrupt request can be serviced, the following conditions must be met: ? interrupt processing must be enabled (ei, sym.3 = "1") ? interrupt must be enabled at the interrupt's source (peripheral control register) if all of the above conditions are met, the interrupt request is acknowledged at the end of the instruction cycle. the cpu then initiates an interrupt machine cycle that completes the following processing sequence: 1. reset (clear to "0") the global interrupt enable bit in the sym register (di, sym.3 = "0") to disable all subsequent interrupts. 2. save the program counter and status flags to stack. 3. branch to the interrupt vector to fetch the service routine's address. 4. pass control to the interrupt service routine. when the interrupt service routine is completed, an interrupt return instruction (iret) occurs. the iret restores the pc and status flags and sets sym.3 to "1" (ei), allowing the cpu to process the next interrupt request. generating interrupt vector addresses the interrupt vector area in the rom contains the address of the interrupt service routine. vectored interrupt processing follows this sequence: 1. push the program counter's low-byte value to stack. 2. push the program counter's high -byte value to stack. 3. push the flags register values to stack. 4. fetch the service routine's high-byte address from the vector address 0000h. 5. fetch the service routine's low-byte address from the vector address 0001h. 6. branch to the service routine specified by the 16-bit vector address.
interrupt structure s3c9484/c9488/f9488 5- 4 s3c9484/c9488/f9488 interrupt structure the s3c9484/c9488/f9488 microcontroller has four peripheral interrupt sources: ? timer a match / overflow ? timer b underflow ? p3.3 / p3.4 / p3.5 / p3.6 external interrupt ? watch timer interrupt ? uart transmit interrupt / receive interrupt 0000h 0001h vector pending bits enable/disable source uartpnd.1 uartcon.1 uart receive uartpnd.0 uartcon.0 uart transmit tintpnd.1 sym.3 (ei, di) tintpnd.2 p3pnd.0 p3pnd.1 tacon.2 tbcon.3 p3int.0-.1 p3int.2-.3 timer a overflow timer b underflow p3.3 external interrupt (int0) p3.4 external interrupt (int1) p3pnd.2 p3pnd.3 wtcon.0 tacon.1 timer a match p3int.4-.5 p3int.6-.7 wtcon.1 p3.5 external interrupt (int2) p3.6 external interrupt (int3) watch timer interrupt tintpnd.0 figure 5-3. s3c9484/c9488/f9488 interrupt structure
s3c9484/c9488/f9488 sam88rcri instruct ion set 6- 1 6 sam88rcri instructi on set overview the sam88rcri instruction set is designed to support the large register file. it includes a full complement of 8-bit arithmetic and logic operations. there are 41 instructions. no special i/o instructions are necessary because i/o control and data registers are mapped directly into the register file. flexible instructions for bit addressing, rotate, and shift operations complete the powerful data manipulation capabilities of the sam88rcri instruction set. register addressing to access an individual register, an 8-bit address in the range 0-255 or the 4-bit address of a working register is specified. paired registers can be used to construct 13-bit program memory or data memory addresses. for detailed information about register addressing, please refer to chapter 2, "address spaces". addressing modes there are six addressing modes: register (r), indirect register (ir), indexed (x), direct (da), relative (ra), and immediate (im). for detailed descriptions of these addressing modes, please refer to chapter 3, "addressing modes".
sam88rcri instruction set s3c9484/c9488 /f9488 6- 2 table 6-1. instruction group summary mnemonic operands instruction load instructions clr dst clear ld dst,src load ldc dst,src load program memory lde dst,src load external data memory ldcd dst,src load program memory and decrement lded dst,src load external data memory and decrement ldci dst,src load program memory and increment ldei dst,src load external data memory and increment pop dst pop from stack push src push to stack arithmetic instructions adc dst,src add with carry add dst,src add cp dst,src compare dec dst decrement inc dst increment sbc dst,src subtract with carry sub dst,src subtract logic instructions and dst,src logical and com dst complement or dst,src logical or xor dst,src logical exclusive or
s3c9484/c9488/f9488 sam88rcri instruct ion set 6- 3 table 6-1. instruction group summary (continued) mnemonic operands instruction program control instructions call dst call procedure iret interrupt return jp cc,dst jump on condition code jp dst jump unconditional jr cc,dst jump relative on condition code ret return bit manipulation instructions tcm dst,src test complement under mask tm dst,src test under mask rotate and shift instructions rl dst rotate left rlc dst rotate left through carry rr dst rotate right rrc dst rotate right through carry sra dst shift right arithmetic cpu control instructions ccf complement carry flag di disable interrupts ei enable interrupts idle enter idle mode nop no operation rcf reset carry flag scf set carry flag stop enter stop mode
sam88rcri instruction set s3c9484/c9488 /f9488 6- 4 flags register (flags) the flags register flags contains eight bits that describe the current status of cpu operations. four of these bits, flags.4?flags.7, can be tested and used with conditional jump instructions; flags register can be set or reset by instructions as long as its outcome does not affect the flags, such as, load instruction. logical and arithmetic instructions such as, and, or, xor, add, and sub can affect the flags register. for example, the and instruction updates the zero, sign and overflow flags based on the outcome of the and instruction. if the and instruction uses the flags register as the destination, then simultaneously, two write will occur to the flags register producing an unpredictable result. system flags register (flags) d5h, r/w .7 .6 .5 .4 .3 .2 .1 .0 msb lsb carry flag (c) zero flag (z) sign flag (s) overflow flag (v) not mapped figure 6-1. system flags register (flags) flag descriptions overflow flag (flags.4, v) the v flag is set to "1" when the result of a two's-complement operation is greater than + 127 or less than ? 128. it is also cleared to "0" following logic operations. sign flag (flags.5, s) following arithmetic, logic, rotate, or shift operations, the sign bit identifies the state of the msb of the result. a logic zero indicates a positive number and a logic one indicates a negative number. zero flag (flags.6, z) for arithmetic and logic operations, the z flag is set to "1" if the result of the operation is zero. for operations that test register bits, and for shift and rotate operations, the z flag is set to "1" if the result is logic zero. carry flag (flags.7, c) the c flag is set to "1" if the result from an arithmetic operation generates a carry-out from or a borrow to the bit 7 position (msb). after rotate and shift operations, it contains the last value shifted out of the specified register. program instructions can set, clear, or complement the carry flag.
s3c9484/c9488/f9488 sam88rcri instruct ion set 6- 5 instruction set notation table 6-2. flag notation conventions flag description c carry flag z zero flag s sign flag v overflow flag 0 cleared to logic zero 1 set to logic one * set or cleared according to operation ? value is unaffected x value is undefined table 6-3. instruction set symbols symbol description dst destination operand src source operand @ indirect register address prefix pc program counter flags flags register (d5h) # immediate operand or register address prefix h hexadecimal number suffix d decimal number suffix b binary number suffix opc opcode
sam88rcri instruction set s3c9484/c9488 /f9488 6- 6 table 6-4. instruction notation conventions notation description actual operand range cc condition code see list of condition codes in table 6-6. r working register only rn (n = 0?15) rr working register pair rrp (p = 0, 2, 4, ..., 14) r register or working register reg or rn (reg = 0?255, n = 0?15) rr register pair or working register pair reg or rrp (reg = 0?254, even number only, where p = 0, 2, ..., 14) ir indirect working register only @rn (n = 0?15) ir indirect register or indirect working register @rn or @reg (reg = 0?255, n = 0?15) irr indirect working register pair only @rrp (p = 0, 2, ..., 14) irr indirect register pair or indirect working register pair @rrp or @reg (reg = 0?254, even only, where p = 0, 2, ..., 14) x indexed addressing mode #reg[rn] (reg = 0?255, n = 0?15) xs indexed (short offset) addressing mode #addr[rrp] (addr = range ? 128 to + 127, where p = 0, 2, ..., 14) xl indexed (long offset) addressing mode #addr [rrp] (addr = range 0?8191, where p = 0, 2, ..., 14) da direct addressing mode addr (addr = range 0?8191) ra relative addressing mode addr (addr = number in the range + 127 to ? 128 that is an offset relative to the address of the next instruction) im immediate addressing mode #data (data = 0?255)
s3c9484/c9488/f9488 sam88rcri instruct ion set 6- 7 table 6-5. opcode quick reference opcode map lower nibble (hex) ? 0 1 2 3 4 5 6 7 u 0 dec r1 dec ir1 add r1,r2 add r1,ir2 add r2,r1 add ir2,r1 add r1,im p 1 rlc r1 rlc ir1 adc r1,r2 adc r1,ir2 adc r2,r1 adc ir2,r1 adc r1,im p 2 inc r1 inc ir1 sub r1,r2 sub r1,ir2 sub r2,r1 sub ir2,r1 sub r1,im e 3 jp irr1 sbc r1,r2 sbc r1,ir2 sbc r2,r1 sbc ir2,r1 sbc r1,im r 4 or r1,r2 or r1,ir2 or r2,r1 or ir2,r1 or r1,im 5 pop r1 pop ir1 and r1,r2 and r1,ir2 and r2,r1 and ir2,r1 and r1,im n 6 com r1 com ir1 tcm r1,r2 tcm r1,ir2 tcm r2,r1 tcm ir2,r1 tcm r1,im i 7 push r2 push ir2 tm r1,r2 tm r1,ir2 tm r2,r1 tm ir2,r1 tm r1,im b 8 ld r1, x, r2 b 9 rl r1 rl ir1 ld r2, x, r1 l a cp r1,r2 cp r1,ir2 cp r2,r1 cp ir2,r1 cp r1,im ldc r1, irr2, xl e b clr r1 clr ir1 xor r1,r2 xor r1,ir2 xor r2,r1 xor ir2,r1 xor r1,im ldc r2, irr2, xl c rrc r1 rrc ir1 ldc r1,irr2 ld r1, ir2 h d sra r1 sra ir1 ldc r2,irr1 ld ir1,im ld ir1, r2 e e rr r1 rr ir1 ldcd r1,irr2 ldci r1,irr2 ld r2,r1 ld r2,ir1 ld r1,im ldc r1, irr2, xs x f call irr1 ld ir2,r1 call da1 ldc r2, irr1, xs
sam88rcri instruction set s3c9484/c9488 /f9488 6- 8 table 6-5. opcode quick reference (continued) opcode map lower nibble (hex) ? 8 9 a b c d e f u 0 ld r1,r2 ld r2,r1 jr cc,ra ld r1,im jp cc,da inc r1 p 1 p 2 e 3 r 4 5 n 6 idle i 7 stop b 8 di b 9 ei l a ret e b iret c rcf h d scf e e ccf x f ld r1,r2 ld r2,r1 jr cc,ra ld r1,im jp cc,da inc r1 nop
s3c9484/c9488/f9488 sam88rcri instruct ion set 6- 9 condition codes the opcode of a conditional jump always contains a 4-bit field called the condition code (cc). this specifies under which conditions it is to execute the jump. for example, a conditional jump with the condition code for "equal" after a compare operation only jumps if the two operands are equal. condition codes are listed in table 6-6. the carry (c), zero (z), sign (s), and overflow (v) flags are used to control the operation of conditional jump instructions. table 6-6. condition codes binary mnemonic description flags set 0000 f always false ? 1000 t always true ? 0111 (1) c carry c = 1 1111 (1) nc no carry c = 0 0110 (1) z zero z = 1 1110 (1) nz not zero z = 0 1101 pl plus s = 0 0101 mi minus s = 1 0100 ov overflow v = 1 1100 nov no overflow v = 0 0110 (1) eq equal z = 1 1110 (1) ne not equal z = 0 1001 ge greater than or equal (s xor v) = 0 0001 lt less than (s xor v) = 1 1010 gt greater than (z or (s xor v)) = 0 0010 le less than or equal (z or (s xor v)) = 1 1111 (1) uge unsigned greater than or equal c = 0 0111 (1) ult unsigned less than c = 1 1011 ugt unsigned greater than (c = 0 and z = 0) = 1 0011 ule unsigned less than or equal (c or z) = 1 notes: 1. it indicates condition codes that are related to two different mnemonics but which test the same flag. for example, z and eq are both true if the zero flag (z) is set, but after an add instruction, z would probably be used; after a cp instruction, however, eq would probably be used. 2. for operations involving unsigned numbers, the special condition codes uge, ult, ugt, and ule must be used.
sam88rcri instruction set s3c9484/c9488 /f9488 6- 10 instruction descriptions this section contains detailed information and programming examples for each instruction in the sam88rcri instruction set. information is arranged in a consistent format for improved readability and for fast referencing. the following information is included in each instruction description: ? instruction name (mnemonic) ? full instruction name ? source/destination format of the instruction operand ? shorthand notation of the instruction's operation ? textual description of the instruction's effect ? specific flag settings affected by the instruction ? detailed description of the instruction's format, execution time, and addressing mode(s) ? programming example(s) explaining how to use the instruction
s3c9484/c9488/f9488 sam88rcri instruct ion set 6- 11 adc ? add with carry adc dst,src operation: dst _ dst + src + c the source operand, along with the setting of the carry flag, is added to the destination operand and the sum is stored in the destination. the contents of the source are unaffected. two's-complement addition is performed. in multiple precision arithmetic, this instruction permits the carry from the addition of low-order operands to be carried into the addition of high-order operands. flags: c: set if there is a carry from the most significant bit of the result; cleared otherwise. z: set if the resu lt is "0"; cleared otherwise. s: set if the result is negative; cleared otherwise. v: set if arithmetic overflow occurs, that is, if both operands are of the same sign and the result is of the opposite sign; cleared otherwise. format: bytes cycles opcode (hex) addr mode dst src opc dst | src 2 4 12 r r 6 13 r lr opc src dst 3 6 14 r r 6 15 r ir opc dst src 3 6 16 r im examples: given: r1 = 10h, r2 = 03h, c flag = "1", register 01h = 20h, register 02h = 03h, and register 03h = 0ah: adc r1,r2 ? r1 = 14h, r2 = 03h adc r1,@r2 ? r1 = 1bh, r2 = 03h adc 01h,02h ? register 01h = 24h, register 02h = 03h adc 01h,@02h ? register 01h = 2bh, register 02h = 03h adc 01h,#11h ? register 01h = 32h in the first example, destination register r1 contains the value 10h, the carry flag is set to "1", and the source working register r2 contains the value 03h. the statement "adc r1,r2" adds 03h and the carry flag value ("1") to the destination value 10h, leaving 14h in register r1.
sam88rcri instruction set s3c9484/c9488 /f9488 6- 12 add ? add add dst,src operation: dst _ dst + src the source operand is added to the destination operand and the sum is stored in the destination. the contents of the source are unaffected. two's-complement addition is performed. flags: c: set if there is a carry from the most significant bit of the result; cleared otherwise. z: set if the result is "0"; cleared otherwise. s: set if the result is negative; cleared otherwise. v: set if arithmetic overflow occurred, that is, if both operands are of the same sign and the result is of the opposite sign; cleared otherwise. format: bytes cycles opcode (hex) addr mode dst src opc dst | src 2 4 02 r r 6 03 r lr opc src dst 3 6 04 r r 6 05 r ir opc dst src 3 6 06 r im examples: given: r1 = 12h, r2 = 03h, register 01h = 21h, register 02h = 03h, register 03h = 0ah: add r1,r2 ? r1 = 15h, r2 = 03h add r1,@r2 ? r1 = 1ch, r2 = 03h add 01h,02h ? register 01h = 24h, register 02h = 03h add 01h,@02h ? register 01h = 2bh, register 02h = 03h add 01h,#25h ? register 01h = 46h in the first example, destination working register r1 contains 12h and the source working register r2 contains 03h. the statement "add r1,r2" adds 03h to 12h, leaving the value 15h in register r1.
s3c9484/c9488/f9488 sam88rcri instruct ion set 6- 13 and ? logical and and dst,src operation: dst _ dst and src the source operand is logically anded with the destination operan d. the result is stored in the destination. the and operation results in a "1" bit being stored whenever the corresponding bits in the two operands are both logic ones; otherwise a "0" bit value is stored. the contents of the source are unaffected. flags: c: unaffected. z: set if the result is "0"; cleared otherwise. s: set if the result bit 7 is set; cleared otherwise. v: always cleared to "0". format: bytes cycles opcode (hex) addr mode dst src opc dst | src 2 4 52 r r 6 53 r lr opc src dst 3 6 54 r r 6 55 r ir opc dst src 3 6 56 r im examples: given: r1 = 12h, r2 = 03h, register 01h = 21h, register 02h = 03h, register 03h = 0ah: and r1,r2 ? r1 = 02h, r2 = 03h and r1,@r2 ? r1 = 02h, r2 = 03h and 01h,02h ? register 01h = 01h, register 02h = 03h and 01h,@02h ? register 01h = 00h, register 02h = 03h and 01h,#25h ? register 01h = 21h in the first example, destination working register r1 contains the value 12h and the source working register r2 contains 03h. the statement "and r1,r2" logically ands the source operand 03h with the destination operand value 12h, leaving the value 02h in register r1.
sam88rcri instruction set s3c9484/c9488 /f9488 6- 14 call ? call procedure call dst operation: sp ? sp ? 1 @sp ? pcl sp ? sp ?1 @sp ? pch pc ? dst the current contents of the program counter are pushed onto the top of the stack. the program counter value used is the address of the first instruction following the call instruction. the specified destination address is then loaded into the program counter and points to the first instruction of a procedure. at the end of the procedure the return instruction (ret) can be used to return to the original program flow. ret pops the top of the stack back into the program counter. flags: no flags are affected. format: bytes cycles opcode (hex) addr mode dst opc dst 3 14 f6 da opc dst 2 12 f4 irr examples: given: r0 = 15h, r1 = 21h, pc = 1a47h, and sp = 0b2h: call 1521h ? sp = 0b0h (memory locations 00h = 1ah, 01h = 4ah, where 4ah is the address that follows the instruction.) call @rr0 ? sp = 0b0h (00h = 1ah, 01h = 49h) in the first example, if the program counter value is 1a47h and the stack pointer contains the value 0b2h, the statement "call 1521h" pushes the current pc value onto the top of the stack. the stack pointer now points to memory location 00h. the pc is then loaded with the value 1521h, the address of the first instruction in the program sequence to be executed. if the contents of the program counter and stack pointer are the same as in the first example, the statement "call @rr0" produces the same result except that the 49h is stored in stack location 01h (because the two-byte instruction format was used). the pc is then loaded with the value 1521h, the address of the first instruction in the program sequence to be executed.
s3c9484/c9488/f9488 sam88rcri instruct ion set 6- 15 ccf ? complement carry flag ccf operation: c _ not c the carry flag (c) is complemented. if c = "1", the value of the carry flag is changed to logic zero; if c = "0", the value of the carry flag is changed to logic one. flags: c: complemented. no other flags are affected. format: bytes cycles opcode (hex) opc 1 4 ef example: given: the carry flag = "0": ccf if the carry flag = "0", the ccf instruction complements it in the flags register (0d5h), changing its value from logic zero to logic one.
sam88rcri instruction set s3c9484/c9488 /f9488 6- 16 clr ? clear clr dst operation: dst _ "0" the destination location is cleared to "0". flags: no flags are affected. format: bytes cycles opcode (hex) addr mode dst opc dst 2 4 b0 r 4 b1 ir examples: given: register 00h = 4fh, register 01h = 02h, and register 02h = 5eh: clr 00h ? register 00h = 00h clr @01h ? register 01h = 02h, register 02h = 00h in register (r) addressing mode, the statement "clr 00h" clears the destination register 00h value to 00h. in the second example, the statement "clr @01h" uses indirect register (ir) addressing mode to clear the 02h register value to 00h.
s3c9484/c9488/f9488 sam88rcri instruct ion set 6- 17 com ? complement com dst operation: dst _ not dst the contents of the destination location are complemented (one's complement); all "1s" are changed to "0s", and vice-versa. flags: c: unaffected. z: set if the result is "0"; cleared otherwise. s: set if the result bit 7 is set; cleared otherwise. v: always reset to "0". format: bytes cycles opcode (hex) addr mode dst opc dst 2 4 60 r 4 61 ir examples: given: r1 = 07h and regis ter 07h = 0f1h: com r1 ? r1 = 0f8h com @r1 ? r1 = 07h, register 07h = 0eh in the first example, destination working register r1 contains the value 07h (00000111b). the statement "com r1" complements all the bits in r1: all logic ones are changed to logic zeros, and vice-versa, leaving the value 0f8h (11111000b). in the second example, indirect register (ir) addressing mode is used to complement the value of destination register 07h (11110001b), leaving the new value 0eh (00001110b).
sam88rcri instruction set s3c9484/c9488 /f9488 6- 18 cp ? compare cp dst,src operation: dst ? src the source operand is compared to (subtracted from) the destination operand, and the appropriate flags are set accordingly. the contents of both operands are unaffected by the comparison. flags: c: set if a "borrow" occurred (src > dst); cleared otherwise. z: set if the result is "0"; cleared otherwise. s: set if the result is negative; cleared otherwise. v: set if arithmetic overflow occurred, that is, if the operands were of opposite signs and the sign of the result is of the same as the sign of the source operand; cleared otherwise. format: bytes cycles opcode (hex) addr mode dst src opc dst | src 2 4 a2 r r 6 a3 r lr opc src dst 3 6 a4 r r 6 a5 r ir opc dst src 3 6 a6 r im examples: 1. given: r1 = 02h and r2 = 03h: cp r1,r2 ? set the c and s flags destination working register r1 contains the value 02h and source register r2 contains the value 03h. the statement "cp r1,r2" subtracts the r2 value (source/subtrahend) from the r1 value (destination/minuend). because a "borrow" occurs and the difference is negative, c and s are "1". 2. given: r1 = 05h and r2 = 0ah: cp r1,r2 jp uge,skip inc r1 skip ld r3,r1 in this example, destination working register r1 contains the value 05h which is less than the contents of the source working register r2 (0ah). the statement "cp r1,r2" generates c = "1" and the jp instruction does not jump to the skip location. after the statement "ld r3,r1" executes, the value 06h remains in working register r3.
s3c9484/c9488/f9488 sam88rcri instruct ion set 6- 19 dec ? decrement dec dst operation: dst _ dst ? 1 the contents of the destination operand are decremented by one. flags: c: unaffected. z: set if the result is "0"; cleared otherwise. s: set if result is negative; cleared otherwise. v: set if arithmetic overflow occurred, that is, dst value is ? 128 (80h) and result value is + 127 (7fh); cleared otherwise. format: bytes cycles opcode (hex) addr mode dst opc dst 2 4 00 r 4 01 ir examples: given: r1 = 03h and register 03h = 10h: dec r1 ? r1 = 02h dec @r1 ? register 03h = 0fh in the first example, if working register r1 contains the value 03h, the statement "dec r1" decrements the hexadecimal value by one, leaving the value 02h. in the second example, the statement "dec @r1" decrements the value 10h contained in the destination register 03h by one, leaving the value 0fh.
sam88rcri instruction set s3c9484/c9488 /f9488 6- 20 di ? disable interrupts di operation: sym (3) _ 0 bit zero of the system mode register, sym.3, is cleared to "0", globally disabling all interrupt processing. interrupt requests will continue to set their respective interrupt pending bits, but the cpu will not service them while interrupt processing is disabled. flags: no flags are affected. format: bytes cycles opcode (hex) opc 1 4 8f example: given: sym = 08h: di if the value of the sym register is 08h, the statement "di" leaves the new value 00h in the register and clears sym.3 to "0", disabling interrupt processing.
s3c9484/c9488/f9488 sam88rcri instruct ion set 6- 21 ei ? enable interrupts ei operation: sym (3) _ 1 an ei instruction sets bit 3 of the system mode register, sym.3 to "1". this allows interrupts to be serviced as they occur. if an interrupt's pending bit was set while interrupt processing was disabled (by executing a di instruction), it will be serviced when you execute the ei instruction. flags: no flags are affected. format: bytes cycles opcode (hex) opc 1 4 9f example: given: sym = 00h: ei if the sym register contains the value 00h, that is, if interrupts are currently disabled, the statement "ei" sets the sym register to 08h, enabling all interrupts. (sym.3 is the enable bit for global interrupt processing.)
sam88rcri instruction set s3c9484/c9488 /f9488 6- 22 idle ? idle operation idle operation: the idle instruction stops the cpu clock while allowing system clock oscillation to continue. idle mode can be released by an interrupt request (irq) or an external reset operation. flags: no flags are affected. format: bytes cycles opcode (hex) addr mode dst src opc 1 4 6f ? ? example: the instruction idle nop nop nop stops the cpu clock but not the system clock.
s3c9484/c9488/f9488 sam88rcri instruct ion set 6- 23 inc ? increment inc dst operation: dst _ dst + 1 the contents of the destination operand are incremented by one. flags: c: unaffected. z: set if the result is "0"; cleared otherwise. s: set if the result is negative; cleared otherwise. v: set if arithmetic overflow occurred, that is dst value is + 127 (7fh) and result is ? 128 (80h); cleared otherwise. format: bytes cycles opcode (hex) addr mode dst dst | opc 1 4 re r r = 0 to f opc dst 2 4 20 r 4 21 ir examples: given: r0 = 1bh, register 00h = 0ch, and register 1bh = 0fh: inc r0 ? r0 = 1ch inc 00h ? register 00h = 0dh inc @r0 ? r0 = 1bh, register 01h = 10h in the first example, if destination working register r0 contains the value 1bh, the statement "inc r0" leaves the value 1ch in that same register. the next example shows the effect an inc instruction has on register 00h, assuming that it contains the value 0ch. in the third example, inc is used in indirect register (ir) addressing mode to increment the value of register 1bh from 0fh to 10h.
sam88rcri instruction set s3c9484/c9488 /f9488 6- 24 iret ? interrupt return iret iret operation: flags _ @sp sp _ sp + 1 pc _ @sp sp _ sp + 2 sym(2) _ 1 this instruction is used at the end of an interrupt service routine. it restores the flag register and the program counter. it also re-enables global interrupts. flags: all flags are restored to their original settings (that is, the settings before the interrupt occurred). format: iret (normal) bytes cycles opcode (hex) opc 1 10 bf 12
s3c9484/c9488/f9488 sam88rcri instruct ion set 6- 25 jp ? jump jp cc,dst (conditional) jp dst (unconditional) operation: if cc is true, pc _ dst the conditional jump instruction transfers program control to the destination address if the condition specified by the condition code (cc) is true; otherwise, the instruction following the jp instruction is executed. the unconditional jp simply replaces the contents of the pc with the contents of the specified register pair. control then passes to the statement addressed by the pc. flags: no flags are affected. format: (1) (2) bytes cycles opcode (hex) addr mode dst cc | opc dst 3 8 ccd da cc = 0 to f opc dst 2 8 30 irr notes : 1. the 3-byte format is used for a conditional jump and the 2-byte format for an unconditional jump. 2. in the first byte of the three-byte instruction format (conditional jump), the condition code and the op code are both four bits. examples: given: the carry flag (c) = "1", register 00 = 01h, and register 01 = 20h: jp c,label_w ? label_w = 1000h, pc = 1000h jp @00h ? pc = 0120h the first example shows a conditional jp. assuming that the carry flag is set to "1", the statement "jp c,label_w" replaces the contents of the pc with the value 1000h and transfers control to that location. had the carry flag not been set, control would then have passed to the statement immediately following the jp instruction. the second example shows an unconditional jp. the statement "jp @00" replaces the contents of the pc with the contents of the register pair 00h and 01h, leaving the value 0120h.
sam88rcri instruction set s3c9484/c9488 /f9488 6- 26 jr ? jump relative jr cc,dst operation: if cc is true, pc _ pc + dst if the condition specified by the condition code (cc) is true, the relative address is added to the program counter and control passes to the statement whose address is now in the program counter; otherwise, the instruction following the jr instruction is executed (see list of condition codes). the range of the relative address is + 127, ? 128, and the original value of the program counter is taken to be the address of the first instruction byte following the jr statement. flags: no flags are affected. format: (note) bytes cycles opcode (hex) addr mode dst cc | opc dst 2 6 ccb ra cc = 0 to f note : in the first byte of the two-byte instruction format, the condition code and the op code are each four bits. example: given: the carry flag = "1" and label_x = 1ff7h: jr c,label_x ? pc = 1ff7h if the carry flag is set (that is, if the condition code is true), the statement "jr c,label_x" will pass control to the statement whose address is now in the pc. otherwise, the program instruction following the jr would be executed.
s3c9484/c9488/f9488 sam88rcri instruct ion set 6- 27 ld ? load ld dst,src operation: dst _ src the contents of the source are loaded into the destination. the source's contents are unaffected. flags: no flags are affected. format: bytes cycles opcode (hex) addr mode dst src dst | opc src 2 4 rc r im 4 r8 r r src | opc dst 2 4 r9 r r r = 0 to f opc dst | src 2 4 c7 r lr 4 d7 ir r opc src dst 3 6 e4 r r 6 e5 r ir opc dst src 3 6 e6 r im 6 d6 ir im opc src dst 3 6 f5 ir r opc dst | src x 3 6 87 r x [r] opc src | dst x 3 6 97 x [r] r
sam88rcri instruction set s3c9484/c9488 /f9488 6- 28 ld ? load ld (continued) examples: given: r0 = 01h, r1 = 0ah, register 00h = 01h, register 01h = 20h, register 02h = 02h, loop = 30h, and register 3ah = 0ffh: ld r0,#10h ? r0 = 10h ld r0,01h ? r0 = 20h, register 01h = 20h ld 01h,r0 ? register 01h = 01h, r0 = 01h ld r1,@r0 ? r1 = 20h, r0 = 01h ld @r0,r1 ? r0 = 01h, r1 = 0ah, register 01h = 0ah ld 00h,01h ? register 00h = 20h, register 01h = 20h ld 02h,@00h ? register 02h = 20h, register 00h = 01h ld 00h,#0ah ? register 00h = 0ah ld @00h,#10h ? register 00h = 01h, register 01h = 10h ld @00h,02h ? register 00h = 01h, register 01h = 02, register 02h = 02h ld r0,#loop[r1] ? r0 = 0ffh, r1 = 0ah ld #loop[r0],r1 ? register 31h = 0ah, r0 = 01h, r1 = 0ah
s3c9484/c9488/f9488 sam88rcri instruct ion set 6- 29 ldc/lde ? load memory ldc/lde dst,src operation: dst _ src this instruction loads a byte from program or data memory into a working register or vice-versa. the source values are unaffected. ldc refers to program memory and lde to data memory. the assembler makes "irr" or "rr" values an even number for program memory and odd an odd number for data memory. flags: no flags are affected. format: bytes cycles opcode (hex) addr mode dst src 1. opc dst | src 2 10 c3 r irr 2. opc src | dst 2 10 d3 irr r 3. opc dst | src xs 3 12 e7 r xs [rr] 4. opc src | dst xs 3 12 f7 xs [rr] r 5. opc dst | src xl l xl h 4 14 a7 r xl [rr] 6. opc src | dst xl l xl h 4 14 b7 xl [rr] r 7. opc dst | 0000 da l da h 4 14 a7 r da 8. opc src | 0000 da l da h 4 14 b7 da r 9. opc dst | 0001 da l da h 4 14 a7 r da 10. opc src | 0001 da l da h 4 14 b7 da r notes : 1. the source (src) or working register pair [rr] for formats 5 and 6 cannot use register pair 0?1. 2. for formats 3 and 4, the destination address "xs [rr]" and the source address "x s [rr]" are each one byte. 3. for formats 5 and 6, the destination address "xl [rr]" and the source address "xl [rr]" are each two bytes. 4. the da and r source values for formats 7 and 8 are used to address program memory; the second set of values, used in formats 9 and 10, are used to address data memory.
sam88rcri instruction set s3c9484/c9488 /f9488 6- 30 ldc/lde ? load memory ldc/lde (continued) examples: given: r0 = 11h, r1 = 34h, r2 = 01h, r3 = 04h, r4 = 00h, r5 = 60h; program memory locations 0061 = aah, 0103h = 4fh, 0104h = 1a, 0105h = 6dh, and 1104h = 88h. external data memory locations 0061h = bbh, 0103h = 5fh, 0104h = 2ah, 0105h = 7dh, and 1104h = 98h: ldc r0,@rr2 ; r0 _ contents of program memory location 0104h ; r0 = 1ah, r2 = 01h, r3 = 04h lde r0,@rr2 ; r0 _ contents of external data memory location 0104h ; r0 = 2ah, r2 = 01h, r3 = 04h ldc (note) @rr2,r0 ; 11h (contents of r0) is loaded into program memory ; location 0104h (rr2), ; working registers r0, r2, r3 _ no change lde @rr2,r0 ; 11h (contents of r0) is loaded into external data memory ; location 0104h (rr2), ; working registers r0, r2, r3 _ no change ldc r0,#01h[rr4] ; r0 _ contents of program memory location 0061h ; (01h + rr4), ; r0 = aah, r2 = 00h, r3 = 60h lde r0,#01h[rr4] ; r0 _ contents of external data memory location 0061h ; (01h + rr4), r0 = bbh, r4 = 00h, r5 = 60h ldc (note) #01h[rr4],r0 ; 11h (contents of r0) is loaded into program memory location ; 0061h (01h + 0060h) lde #0 1h[rr4],r0 ; 11h (contents of r0) is loaded into external data memory ; location 0061h (01h + 0060h) ldc r0,#1000h[rr2] ; r0 _ contents of program memory location 1104h ; (1000h + 0104h), r0 = 88h, r2 = 01h, r3 = 04h lde r0,#1000h[rr2] ; r0 _ contents of external data memory location 1104h ; (1000h + 0104h), r0 = 98h, r2 = 01h, r3 = 04h ldc r0,1104h ; r0 _ contents of program memory location 1104h, r0 = 88h lde r0,1104h ; r0 _ contents of external data memory location 1104h, ; r0 = 98h ldc (note) 1105h,r0 ; 11h (contents of r0) is loaded into program memory location ; 1105h, (1105h) _ 11h lde 1105h,r0 ; 11h (contents of r0) is loaded into external data memory ; location 1105h, (1105h) _ 11h note : these instructions are not supported by masked rom type devices.
s3c9484/c9488/f9488 sam88rcri instruct ion set 6- 31 ldcd/lded ? load memory and decrement ldcd/lded dst,src operation: dst _ src rr _ rr ? 1 these instructions are used for user stacks or block transfers of data from program or da ta memory to the register file. the address of the memory location is specified by a working register pair. the contents of the source location are loaded into the destination location. the memory address is then decremented. the contents of the source are unaffected. ldcd references program memory and lded references external data memory. the assembler makes "irr" an even number for program memory and an odd number for data memory. flags: no flags are affected. format: bytes cycles opcode (hex) addr mode dst src opc dst | src 2 10 e2 r irr examples: given: r6 = 10h, r7 = 33h, r8 = 12h, program memory location 1033h = 0cdh, and external data memory location 1033h = 0ddh: ldcd r8,@rr6 ; 0cdh (contents of program memory location 1033h) is loaded ; into r8 and rr6 is decremented by one ; r8 = 0cdh, r6 = 10h, r7 = 32h (rr6 _ rr6 ? 1) lded r8,@rr6 ; 0ddh (contents of data memory location 1033h) is loaded ; into r8 and rr6 is decremented by one (rr6 _ rr6 ? 1) ; r8 = 0ddh, r6 = 10h, r7 = 32h
sam88rcri instruction set s3c9484/c9488 /f9488 6- 32 ldci/ldei ? load memory and increment ldci/ldei dst,src operation: dst _ src rr _ rr + 1 these instructions are used for user stacks or block transfers of data from program or data memory to the register file. the address of the memory location is specified by a working register pair. the contents of the source location are loaded into the destination location. the memory address is then incremented automatically. the contents of the source are unaffected. ldci refers to program memory and ldei refers to external data memory. the assembler makes "irr" even for program memory and odd for data memory. flags: no flags are affected. format: bytes cycles opcode (hex) addr mode dst src opc dst | src 2 10 e3 r irr examples: given: r6 = 10h, r7 = 33h, r8 = 12h, program memory locations 1033h = 0cdh and 1034h = 0c5h; external data memory locations 1033h = 0ddh and 1034h = 0d5h: ldci r8,@rr6 ; 0cdh (contents of progra m memory location 1033h) is loaded ; into r8 and rr6 is incremented by one (rr6 _ rr6 + 1) ; r8 = 0cdh, r6 = 10h, r7 = 34h ldei r8,@rr6 ; 0ddh (contents of data memory location 1033h) is loaded ; into r8 and rr6 is incremented by one (rr6 _ rr6 + 1) ; r8 = 0ddh, r6 = 10h, r7 = 34h
s3c9484/c9488/f9488 sam88rcri instruct ion set 6- 33 nop ? no operation nop operation: no action is performed when the cpu executes this instruction. typically, one or more nops are executed in sequence in order to effect a timing delay of variable duration. flags: no flags are affected. format: bytes cycles opcode (hex) opc 1 4 ff example: when the instruction nop is encountered in a program, no operation occurs. instead, there is a delay in instruction execution time.
sam88rcri instruction set s3c9484/c9488 /f9488 6- 34 or ? logical or or dst,src operation: dst _ dst or src the source operand is logically ored with the destination operand and the result is stored in the destination. the contents of the source are unaffected. the or operation results in a "1" being stored whenever either of the corresponding bits in the two operands is a "1"; otherwise a "0" is stored. flags: c: unaffected. z: set if the result is "0"; cleared otherwise. s: set if the result bit 7 is set; cleared otherwise. v: always cleared to "0". format: bytes cycles opcode (hex) addr mode dst src opc dst | src 2 4 42 r r 6 43 r lr opc src dst 3 6 44 r r 6 45 r ir opc dst src 3 6 46 r im examples: given: r0 = 15h, r1 = 2ah, r2 = 01h, register 00h = 08h, register 01h = 37h, and register 08h = 8ah: or r0,r1 ? r0 = 3fh, r1 = 2ah or r0,@r2 ? r0 = 37h, r2 = 01h, register 01h = 37h or 00h,01h ? register 00h = 3fh, register 01h = 37h or 01h,@00h ? register 00h = 08h, register 01h = 0bfh or 00h,#02h ? register 00h = 0ah in the first example, if working register r0 contains the value 15h and register r1 the value 2ah, the statement "or r0,r1" logical-ors the r0 and r1 register contents and stores the result (3fh) in destination register r0. the other examples show the use of the logical or instruction with the various addressing modes and formats.
s3c9484/c9488/f9488 sam88rcri instruct ion set 6- 35 pop ? pop from stack pop dst operation: dst _ @sp sp _ sp + 1 the contents of the location addressed by the stack pointer are loaded into the destination. the stack pointer is then incremented by one. flags: no flags affected. format: bytes cycles opcode (hex) addr mode dst opc dst 2 8 50 r 8 51 ir examples: given: register 00h = 01h, r egister 01h = 1bh, sp (0d9h) = 0bbh, and stack register 0bbh = 55h: pop 00h ? register 00h = 55h, sp = 0bch pop @00h ? register 00h = 01h, register 01h = 55h, sp = 0bch in the first example, general register 00h contains the value 01h. the statement "pop 00h" loads the contents of location 0bbh (55h) into destination register 00h and then increments the stack pointer by one. register 00h then contains the value 55h and the sp points to location 0bch.
sam88rcri instruction set s3c9484/c9488 /f9488 6- 36 push ? push to stack push src operation: sp _ sp ? 1 @sp _ src a push instruction decrements the stack pointer value and loads the contents of the source (src) into the location addressed by the decremented stack pointer. the operation then adds the new value to the top of the stack. flags: no flags are affected. format: bytes cycles opcode (hex) addr mode dst opc src 2 8 70 r 8 71 ir examples: given: register 40h = 4fh, register 4fh = 0aah, sp = 0c0h: push 40h ? register 40h = 4fh, stack register 0bfh = 4fh, sp = 0bfh push @40h ? register 40h = 4fh, register 4fh = 0aah, stack register 0bfh = 0aah, sp = 0bfh in the first example, if the stack pointer contains the value 0c0h, and general register 40h the value 4fh, the statement "push 40h" decrements the stack pointer from 0c0 to 0bfh. it then loads the contents of register 40h into location 0bfh. register 0bfh then contains the value 4fh and sp points to location 0bfh.
s3c9484/c9488/f9488 sam88rcri instruct ion set 6- 37 rcf ? reset carry flag rcf rcf operation: c _ 0 the carry flag is cleared to logic zero, regardless of its previous value. flags: c: cleared to "0". no other flags are affected. format: bytes cycles opcode (hex) opc 1 4 cf example: given: c = "1" or "0": the instruction rcf clears the carry flag (c) to logic zero.
sam88rcri instruction set s3c9484/c9488 /f9488 6- 38 ret ? return ret operation: pc _ @sp sp _ sp + 2 the ret instruction is normally used to return to the previously executing procedure at the end of a procedure entered by a call instruction. the contents of the location addressed by the stack pointer are popped into the program counter. the next statement that is executed is the one that is addressed by the new program counter value. flags: no flags are affected. format: bytes cycles opcode (hex) opc 1 8 af 10 example: given: sp = 0bch, (sp) = 101ah, and pc = 1234: ret ? pc = 101ah, sp = 0beh the statement "ret" pops the contents of stack pointer location 0bch (10h) into the high byte of the program counter. the stack pointer then pops the value in location 0bdh (1ah) into the pc's low byte and the instruction at location 101ah is executed. the stack pointer now points to memory location 0beh.
s3c9484/c9488/f9488 sam88rcri instruct ion set 6- 39 rl ? rotate left rl dst operation: c _ dst (7) dst (0) _ dst (7) dst (n + 1) _ dst (n), n = 0?6 the contents of the destination operand are rotated left one bit position. the initial value of bit 7 is moved to the bit zero (lsb) position and also replaces the carry flag. c 7 0 flags: c: set if the bit rotated from the most significant bit position (bit 7) was "1". z: set if the result is "0"; cleared otherwise. s: set if the result bit 7 is set; cleared otherwise. v: set if arithmetic overflow occurred, that is, if the sign of the destination changed during rotation; cleared otherwise. format: bytes cycles opcode (hex) addr mode dst opc dst 2 4 90 r 4 91 ir examples: given: register 00h = 0aah, register 01h = 02h and register 02h = 17h: rl 00h ? register 00h = 55h, c = "1" rl @01h ? register 01h = 02h, register 02h = 2eh, c = "0" in the first example, if general register 00h contains the value 0aah (10101010b), the statement "rl 00h" rotates the 0aah value left one bit position, leaving the new value 55h (01010101b) and setting the carry and overflow flags.
sam88rcri instruction set s3c9484/c9488 /f9488 6- 40 rlc ? rotate left through carry rlc dst operation: dst (0) _ c c _ dst (7) dst (n + 1) _ dst (n), n = 0?6 the contents of the destination operand with the ca rry flag are rotated left one bit position. the initial value of bit 7 replaces the carry flag (c); the initial value of the carry flag replaces bit zero. c 7 0 flags: c: set if the bit rotated from the most significant bit position (bit 7) was "1". z: set if the result is "0"; cleared otherwise. s: set if the result bit 7 is set; cleared otherwise. v: set if arithmetic overflow occurred, that is, if the sign of the destination changed during rotation; cleared otherwise. format: bytes cycles opcode (hex) addr mode dst opc dst 2 4 10 r 4 11 ir examples: given: register 00h = 0aah, register 01h = 02h, and register 02h = 17h, c = "0": rlc 00h ? register 00h = 54h, c = "1" rlc @01h ? register 01h = 02h, register 02h = 2eh, c = "0" in the first example, if general register 00h has the value 0aah (10101010b), the statement "rlc 00h" rotates 0aah one bit position to the left. the initial value of bit 7 sets the carry flag and the initial value of the c flag replaces bit zero of register 00h, leaving the value 55h (01010101b). the msb of register 00h resets the carry flag to "1" and sets the overflow flag.
s3c9484/c9488/f9488 sam88rcri instruct ion set 6- 41 rr ? rotate right rr dst operation: c _ dst (0) dst (7) _ dst (0) dst (n) _ dst (n + 1), n = 0?6 the contents of the destination operand are rotated right one bit position. the initial value of bit zero (lsb) is moved to bit 7 (msb) and also replaces the carry flag (c). c 7 0 flags: c: set if the bit rotated from the least significant bit position (bit zero) was "1". z: set if the result is "0"; cleared otherwise. s: set if the result bit 7 is set; cleared otherwise. v: set if arithmetic overflow occurred, that is, if the sign of the destination changed during rotation; cleared otherwise. format: bytes cycles opcode (hex) addr mode dst opc dst 2 4 e0 r 4 e1 ir examples: given: register 00h = 31h, register 01h = 02h, and register 02h = 17h: rr 00h ? register 00h = 98h, c = "1" rr @01h ? register 01h = 02h, register 02h = 8bh, c = "1" in the first example, if general register 00h contains the value 31h (00110001b), the statement "rr 00h" rotates this value one bit position to the right. the initial value of bit zero is moved to bit 7, leaving the new value 98h (10011000b) in the destination register. the initial bit zero also resets the c flag to "1" and the sign flag and overflow flag are also set to "1".
sam88rcri instruction set s3c9484/c9488 /f9488 6- 42 rrc ? rotate right through carry rrc dst operation: dst (7) _ c c _ dst (0) dst (n) _ dst (n + 1), n = 0?6 the contents of the destination operand and the carry flag are rotated right one bit position. the initial value of bit zero (lsb) replaces the carry flag; the initial value of the carry flag replaces bit 7 (msb). c 7 0 flags: c: set if the bit rotated from the least significant bit position (bit zero) was "1". z: set if the result is "0" cleared otherwise. s: set if the result bit 7 is set; cleared otherwise. v: set if arithmetic overflow occurred, that is, if the sign of the destination changed during rotation; cleared otherwise. format: bytes cycles opcode (hex) addr mode dst opc dst 2 4 c0 r 4 c1 ir examples: given: register 00h = 55h, register 01h = 02h, register 02h = 17h, and c = "0": rrc 00h ? register 00h = 2ah, c = "1" rrc @01h ? register 01h = 02h, register 02h = 0bh, c = "1" in the first example, if general register 00h contains the value 55h (01010101b), the statement "rrc 00h" rotates this value one bit position to the right. the initial value of bit zero ("1") replaces the carry flag and the initial value of the c flag ("1") replaces bit 7. this leaves the new value 2ah (00101010b) in destination register 00h. the sign flag and overflow flag are both cleared to "0".
s3c9484/c9488/f9488 sam88rcri instruct ion set 6- 43 sbc ? subtract with carry sbc dst,src operation: dst _ dst ? src ? c the source operand, along with the current value of the carry flag, is subtracted from the destination operand and the result is stored in the destination. the contents of the source are unaffected. subtraction is performed by adding the two's-complement of the source operand to the destination operand. in multiple precision arithmetic, this instruction permits the carry ("borrow") from the subtraction of the low-order operands to be subtracted from the subtraction of high-order operands. flags: c: set if a borrow occurred (src > dst); cleared otherwise. z: set if the result is "0"; cleared otherwise. s: set if the result is negative; cleared otherwise . v: set if arithmetic overflow occurred, that is, if the operands were of opposite sign and the sign of the result is the same as the sign of the source; cleared otherwise. format: bytes cycles opcode (hex) addr mode dst src opc dst | src 2 4 32 r r 6 33 r lr opc src dst 3 6 34 r r 6 35 r ir opc dst src 3 6 36 r im examples: given: r1 = 10h, r2 = 03h, c = "1", register 01h = 20h, register 02h = 03h, and register 03h = 0ah: sbc r1,r2 ? r1 = 0ch, r2 = 03h sbc r1,@r2 ? r1 = 05h, r2 = 03h, register 03h = 0ah sbc 01h,02h ? register 01h = 1ch, register 02h = 03h sbc 01h,@02h ? register 01h = 15h,register 02h = 03h, register 03h = 0ah sbc 01h,#8ah ? register 01h = 95h; c, s, and v = "1" in the first example, if working register r1 contains the value 10h and register r2 the value 03h, the statement "sbc r1,r2" subtracts the source value (03h) and the c flag value ("1") from the destination (10h) and then stores the result (0ch) in register r1.
sam88rcri instruction set s3c9484/c9488 /f9488 6- 44 scf ? set carry flag scf operation: c _ 1 the carry flag (c) is set to logic one, regardless of its previous value. flags: c: set to "1". no other flags are affected. format: bytes cycles opcode (hex) opc 1 4 df example: the statement scf sets the carry flag to logic one.
s3c9484/c9488/f9488 sam88rcri instruct ion set 6- 45 sra ? shift right arithmetic sra dst operation: dst (7) _ dst (7) c _ dst (0) dst (n) _ dst (n + 1), n = 0?6 an arithmetic shift-right of one bit position is performed on the destination operand. bit zero (the lsb) replaces the carry flag. the value of bit 7 (the sign bit) is unchanged and is shifted into bit position 6. c 7 0 6 flags: c: set if the bit shifted from the lsb position (bit zero) was "1". z: set if the result is "0"; cleared otherwise. s: set if the result is negative; cleared otherwise. v: always cleared to "0". format: bytes cycles opcode (hex) addr mode dst opc dst 2 4 d0 r 4 d1 ir examples: given: register 00h = 9ah, register 02h = 03h, register 03h = 0bch, and c = "1": sra 00h ? register 00h = 0cd, c = "0" sra @02h ? register 02h = 03h, register 03h = 0deh, c = "0" in the first example, if general register 00h contains the value 9ah (10011010b), the statement "sra 00h" shifts the bit values in register 00h right one bit position. bit zero ("0") clears the c flag and bit 7 ("1") is then shifted into the bit 6 position (bit 7 remains unchanged). this leaves the value 0cdh (11001101b) in destination register 00h.
sam88rcri instruction set s3c9484/c9488 /f9488 6- 46 stop ? stop operation stop operation: the stop instruction stops the both the cpu clock and system clock and causes the microcontroller to enter stop mode. during stop mode, the contents of on-chip cpu registers, peripheral registers, and i/o port control and data registers are retained. stop mode can be released by an external reset operation or external interrupt input. for the reset operation, the reset pin must be held to low level until the required oscillation stabilization interval has elapsed. flags: no flags are affected. format: bytes cycles opcode (hex) addr mode dst src opc 1 4 7f ? ? example: the statement ld stopcon, #0a5h stop nop nop nop halts all microcontroller operations. when stopcon register is not #0a5h value, if you use stop instruction, pc is changed to reset address.
s3c9484/c9488/f9488 sam88rcri instruct ion set 6- 47 sub ? subtract sub dst,src operation: dst _ dst ? src the source operand is subtracted from the destination operand and the result is stored in the destination. the contents of the source are unaffected. subtraction is performed by adding the two's complement of the source operand to the destination operand. flags: c: set if a "borrow" occurred; cleared otherwise. z: set if the result is "0"; cleared otherwise. s: set if the result is negative; cleared otherwise. v: set if arithmetic overflow occurred, that is, if the operands were of opposite signs and the sign of the result is of the same as the sign of the source operand; cleared otherwise. format: bytes cycles opcode (hex) addr mode dst src opc dst | src 2 4 22 r r 6 23 r lr opc src dst 3 6 24 r r 6 25 r ir opc dst src 3 6 26 r im examples: given: r1 = 12h, r2 = 03h, register 01h = 21h, register 02h = 03h, register 03h = 0ah: sub r1,r2 ? r1 = 0fh, r2 = 03h sub r1,@r2 ? r1 = 08h, r2 = 03h sub 01h,02h ? register 01h = 1eh, register 02h = 03h sub 01h,@02h ? register 01h = 17h, register 02h = 03h sub 01h,#90h ? register 01h = 91h; c, s, and v = "1" sub 01h,#65h ? register 01h = 0bch; c and s = "1", v = "0" in the first example, if working register r1 contains the value 12h and if register r2 contains the value 03h, the statement "sub r1,r2" subtracts the source value (03h) from the destination value (12h) and stores the result (0fh) in destination register r1.
sam88rcri instruction set s3c9484/c9488 /f9488 6- 48 tcm ? test complement under mask tcm dst,src operation: (not dst) and src this instruction tests selected bits in the destination operand for a logic one value. the bits to be tested are specified by setting a "1" bit in the corresponding position of the source operand (mask). the tcm statement complements the destination operand, which is then anded with the source mask. the zero (z) flag can then be checked to determine the result. the destination and source operands are unaffected. flags: c: unaffected. z: set if the result is "0"; cleared otherwise. s: set if the result bit 7 is set; cleared otherwise. v: always cleared to "0". format: bytes cycles opcode (hex) addr mode dst src opc dst | src 2 4 62 r r 6 63 r lr opc src dst 3 6 64 r r 6 65 r ir opc dst src 3 6 66 r im examples: given: r0 = 0c7h, r1 = 02h, r2 = 12h, register 00h = 2bh, register 01h = 02h, and register 02h = 23h: tcm r0,r1 ? r0 = 0c7h, r1 = 02h, z = "1" tcm r0,@r1 ? r0 = 0c7h, r1 = 02h, register 02h = 23h, z = "0" tcm 00h,01h ? register 00h = 2bh, register 01h = 02h, z = "1" tcm 00h,@01h ? register 00h = 2bh, register 01h = 02h, register 02h = 23h, z = "1" tcm 00h,#34 ? register 00h = 2bh, z = "0" in the first example, if working register r0 contains the value 0c7h (11000111b) and register r1 the value 02h (00000010b), the statement "tcm r0,r1" tests bit one in the destination register for a "1" value. because the mask value corresponds to the test bit, the z flag is set to logic one and can be tested to determine the result of the tcm operation.
s3c9484/c9488/f9488 sam88rcri instruct ion set 6- 49 tm ? test under mask tm dst,src operation: dst and src this instruction tests selected bits in the destination operand for a logic zero value. the bits to be tested are specified by setting a "1" bit in the corresponding position of the source operand (mask), which is anded with the destination operand. the zero (z) flag can then be checked to determine the result. the destination and source operands are unaffected. flags: c: unaffected. z: set if the result is "0"; cleared otherwise. s: set if the result bit 7 is set; cleared otherwise. v: always reset to "0". format: bytes cycles opcode (hex) addr mode dst src opc dst | src 2 4 72 r r 6 73 r lr opc src dst 3 6 74 r r 6 75 r ir opc dst src 3 6 76 r im examples: given: r0 = 0c7h, r1 = 02h, r2 = 18h, register 00h = 2bh, register 01h = 02h, and register 02h = 23h: tm r0,r1 ? r0 = 0c7h, r1 = 02h, z = "0" tm r0,@r1 ? r0 = 0c7h, r1 = 02h, register 02h = 23h, z = "0" tm 00h,01h ? register 00h = 2bh, register 01h = 02h, z = "0" tm 00h,@01h ? register 00h = 2bh, register 01h = 02h, register 02h = 23h, z = "0" tm 00h,#54h ? register 00h = 2bh, z = "1" in the first example, if working register r0 contains the value 0c7h (11000111b) and register r1 the value 02h (00000010b), the statement "tm r0,r1" tests bit one in the destination register for a "0" value. because the mask value does not match the test bit, the z flag is cleared to logic zero and can be tested to determine the result of the tm operation.
sam88rcri instruction set s3c9484/c9488 /f9488 6- 50 xor ? logical exclusive or xor dst,src operation: dst _ dst xor src the source operand is logically exclusive-ored with the destination operand and the result is stored in the destination. the exclusive-or operation results in a "1" bit being stored whenever the corresponding bits in the operands are different; otherwise, a "0" bit is stored. flags: c: unaffected. z: set if the result is "0"; cleared otherwise. s: set if the result bit 7 is set; cleared otherwise. v: always reset to "0". format: bytes cycles opcode (hex) addr mode dst src opc dst | src 2 4 b2 r r 6 b3 r lr opc src dst 3 6 b4 r r 6 b5 r ir opc dst src 3 6 b6 r im examples: given: r0 = 0c7h, r1 = 02h, r2 = 18h, register 00h = 2bh, register 01h = 02h, and register 02h = 23h: xor r0,r1 ? r0 = 0c5h, r1 = 02h xor r0,@r1 ? r0 = 0e4h, r1 = 02h, register 02h = 23h xor 00h,01h ? register 00h = 29h, register 01h = 02h xor 00h,@01h ? register 00h = 08h, register 01h = 02h, register 02h = 23h xor 00h,#54h ? register 00h = 7fh in the first example, if working register r0 contains the value 0c7h and if register r1 contains the value 02h, the statement "xor r0,r1" logically exclusive-ors the r1 value with the r0 value and stores the result (0c5h) in the destination register r0.
s3c9484/c9488/f9488 clock circuit 7- 1 7 clock circuit overview the clock frequency generation for the s3c9484/c9488/f9488 by an external crystal can range from 1 mhz to 8 mhz. the maximum cpu clock frequency is 8 mhz. the x in and x out pins connect the external oscillator or clock source to the on-chip clock circuit. system clock circuit the system clock circuit has the following components: ? external crystal or ceramic resonator oscillation source (or an external clock source) ? oscillator stop and wake-up functions ? programmable frequency divider for the cpu clock (fxx divided by 1, 2, 8, or 16) ? system clock control register, clkcon ? oscillator control register, osccon and stop control register, stpcon x in x out c1 c2 s3c9484/ c9488/f9488 figure 7-1. main oscillator circuit (crystal or ceramic oscillator) x in x out s3c9484/ c9488/f9488 figure 7-2. main oscillator circuit (rc oscillator)
clock circuit s3c94 84/c9488/f9488 7- 2 clock status during power-down modes the two power-down modes, stop mode and idle mode, affect the system clock as follows: ? in stop mode, the main oscillator is halted. stop mode is released, and the oscillator started, by a reset operation or an external interrupt (with rc delay noise filter), and can be released by internal interrupt too when the sub-system oscillator is running and watch timer is operating with sub-system clock. ? in idle mode, the internal clock signal is gated to the cpu, but not to interrupt structure, timers and timer/ counters. idle mode is released by a reset or by an external or internal interrupt. stop release f x f xt stop sub-system oscillator circuit stop osc inst. f xx cpu stop watch timer timer/counter watch timer (fxx/128) lcd controller a/d converter int selector 1 selector 2 1/8-1/4096 frequency dividing circuit basic timer 1/2 1/8 1/16 1/1 osccon.0 stpcon clkcon.4-.3 idle main-system oscillator circuit osccon.3 osccon.2 figure 7-3. system clock circuit diagram
s3c9484/c9488/f9488 clock circuit 7- 3 system clock control register (clkcon) the system clock control register, clkcon, is located at address d4h. it is read/write addressable and has the following functions: ? oscillator freque ncy divide-by value after the main oscillator is activated, and the fxx/16 (the slowest clock speed) is selected as the cpu clock. if necessary, you can then increase the cpu clock speed to f xx /8, f xx /2, or f xx /1. system clock control register (clkcon) d4h, r/w lsb msb .7 .6 .5 .4 .3 .2 .1 .0 not used not used divide-by selection bits for cpu clock frequency: 00 = f x x/16 01 = f x x/8 10 = f x x/2 11 = f x x/1 (non-divided) oscillator irq wake-up function enable bit: 0 = enable irq for main system oscillator wake-up function 1 = disable irq for main system oscillator wake-up function figure 7-4. system clock control register (clkcon) main/subsystem oscillator selection (osccon) when a main oscillator is selected, users cannot stop operating of a main oscillator by handling the osccon register but sub oscillator can be stopped. if users intend to stop operating of a main oscillator users must use "stop" instruction. when a sub oscillator is selected, users must do the contrary of the above case. note : if a sub oscillator is not used, users must connect it to vss.
clock circuit s3c94 84/c9488/f9488 7- 4 oscillator control register (osccon) d6h, r/w lsb msb .7 .6 .5 .4 .3 .2 .1 .0 not used system clock selection bit: 0 = mainsystem oscillator select 1 = subsystem oscillator select subsystem oscillator control bit: 0 = subsystem oscillator run 1 = subsystem oscillator stop mainsystem oscillator control bit: 0 = mainsystem oscillator run 1 = mainsystem oscillator stop note: when the cpu is operated with fxt (sub-oscillation clock), it is possible to use the stop instruction but in this case before using stop instruction, you must select fxx /128 for basic timer counter input clock . then the oscillation stabilization time is 62.5 ((1/32768) x 128 x 16) ms. here the warm-up time is from the stop release signal activates until the basic timer counter counting start. so the totaly needed oscillation stabilization time will be less than 162.5 ms. not used figure 7-5. oscillator control register (osccon) stop control register (stpcon) d7h, r/w lsb msb .7 .6 .5 .4 .3 .2 .1 .0 stop control bits: other values = disable stop instruction 10100101 = enable stop instruction figure 7-6. stop control register (stpcon)
s3c9484/c9488/f9488 reset and power-down 8- 1 8 reset and power-down system reset overview during a power-on reset, the voltage at v dd goes to high level and the reset pin is forced to low level. the reset signal is input through a schmitt trigger circuit where it is then synchronized with the cpu clock. this procedure brings s3c9484/c9488/f9488 into a known operating status. to allow time for internal cpu clock oscillation to stabilize, the reset pin must be held to low level for a minimum time interval after the power supply comes within tolerance. the minimum required oscillation stabilization time for a reset operation is 1millisecond. whenever a reset occurs during normal operation (that is, when both v dd and reset are high level), the reset pin is forced low and the reset operation starts. all system and peripheral control registers are then reset to their default hardware values. in summary, the following sequence of events occurs during a reset operation: ? interrupt is disabled. ? the watchdog function is enabled. ? ports 0-4 are set to input mode. (except p0.0-2, p3.3-6) ? peripheral control and data registers are disabled and reset to their default hardware values. ? the program counter (pc) is loaded with the program reset address in the rom, 0100h. ? when the programmed oscillation stabil ization time interval has elapsed, the instruction stored in rom location 0100h (and 0101h) is fetched and executed. normal mode reset operation in normal (masked rom) mode, the test pin is tied to v ss . a reset enables access to the 4/8 - kbyte on-chip rom. (the external interface is not automatically configured). note to program the duration of the oscillation stabilization interval, you make the appropriate settings to the basic timer control register, btcon, before entering stop mode. also, if you do not want to use the watchdog timer function (which causes a system reset if a watchdog timer counter overflow occurs), you can disable it by writing '1010b' to the upper nibble of wdtcon.
reset and power-down s3c9484 /c9488/f9488 8- 2 hardware reset values the reset values for cpu and system registers, peripheral control registers, and peripheral data registers following a reset operation. the following notation is used to represent reset values: ? a "1" or a "0" shows the reset bit value as logic one or logic zero, respectively. ? an "x" means that the bit value is undefined after a reset. ? a dash ("?") means that the bit is either not used or not mapped, but read 0 is the bit value. table 8-1. s3c9484/c9488/f9488 register values after reset register name mnemonic address bit values after reset dec hex 7 6 5 4 3 2 1 0 lcd control register lcdcon 208 d0h 0 ? 0 0 0 0 0 0 lcd drive voltage control register lcdvol 209 d1h 0 ? ? ? 0 0 0 0 port 0 pull-up resistor control register p0pur 210 d2h 1 1 1 1 1 1 1 1 port 1 pull-up resistor control register p1pur 211 d3h 1 1 1 1 1 1 1 1 system clock control register clkcon 212 d4h 0 ? ? 0 0 ? ? ? system flags register flags 213 d5h x x x x ? ? ? ? oscillator control register osccon 214 d6h ? ? ? ? 0 0 ? 0 stop control register stpcon 215 d7h 0 0 0 0 0 0 0 0 voltage level detector control register vldcon 216 d8h ? 0 1 0 1 1 0 0 stack pointer register sp 217 d9h x x x x x x x x location dah-dbh are not mapped basic timer control register btcon 220 dch ? ? ? ? 0 0 0 0 basic timer counter register btcnt 221 ddh 0 0 0 0 0 0 0 0 location deh is not mapped system mode register sym 223 dfh ? ? ? ? 0 0 0 0 port 0 data register p0 224 e0h 0 0 0 0 0 0 0 0 port 1 data register p1 225 e1h 0 0 0 0 0 0 0 0 port 2 data register p2 226 e2h 0 0 0 0 0 0 0 0 port 3 data register p3 227 e3h 0 0 0 0 0 0 0 0 port 4 data register p4 228 e4h 0 0 0 0 0 0 0 0 watchdog timer control register wdtcon 229 e5h 0 0 0 0 0 0 0 0 port 0 control high register p0conh 230 e6h 0 0 0 0 0 0 0 0 port 0 control low register p0conl 231 e7h 0 0 0 0 0 0 0 0 port 1 control high register p1conh 232 e8h 0 0 0 0 0 0 0 0 port 1 control low register p1conl 233 e9h 0 0 0 0 0 0 0 0
s3c9484/c9488/f9488 reset and power-down 8- 3 table 8-1. s3c9484/c9488/f9488 registers values after reset (continued) register name mnemonic address bit values after reset dec hex 7 6 5 4 3 2 1 0 port 2 control high register p2conh 234 eah 0 0 0 0 0 0 0 0 port 2 control low register p2conl 235 ebh 0 0 0 0 0 0 0 0 port 3 control high register p3conh 236 ech s s s s s s s s port 3 control low register p3conl 237 edh 0 0 0 0 0 0 0 0 port 3 interrupt control register p3int 238 eeh 0 0 0 0 0 0 0 0 port 3 interrupt pending register p3pnd 239 efh ? ? ? ? 0 0 0 0 port 4 control high register p4conh 240 f0h ? ? 0 0 0 0 0 0 port 4 control low register p4conl 241 f1h 0 0 0 0 0 0 0 0 timer a/b interrupt pending register tintpnd 242 f2h ? ? ? ? ? 0 0 0 timer a control register tacon 243 f3h 0 0 0 0 0 0 0 0 timer a counter register tacnt 244 f4h 0 0 0 0 0 0 0 0 timer a data register tadata 245 f5h 1 1 1 1 1 1 1 1 timer b data register(high byte) tbdatah 246 f6h 1 1 1 1 1 1 1 1 timer b data register(low byte) tbdatal 247 f7h 1 1 1 1 1 1 1 1 timer b control register tbcon 248 f8h 0 0 0 0 0 0 0 0 watch timer control register wtcon 249 f9h 0 0 0 0 0 0 0 0 a/d converter data register(high byte) addatah 250 fah ? ? ? ? ? ? 0 0 a/d converter data register(low byte) addatal 251 fbh 0 0 0 0 0 0 0 0 a/d converter control register adcon 252 fch 0 0 0 0 0 0 0 0 uart control register uartcon 253 fdh 0 0 0 0 0 0 0 0 uart pending register uartpnd 254 feh ? ? 0 0 ? ? 0 0 uart data register udata 255 ffh x x x x x x x x table 8-2. s3c9484/c9488/f9488 registers values after reset (page 1) register name mnemonic address bit values after reset dec hex 7 6 5 4 3 2 1 0 uart baud rate data register(high byte) brdatah 20 14h 1 1 1 1 1 1 1 1 uart baud rate data register(low byte) brdatal 21 15h 1 1 1 1 1 1 1 1 note: ?: not mapped or not used, x: undefined, s: be set by smart option.
reset and power-down s3c9484 /c9488/f9488 8- 4 power-down modes stop mode stop mode is invoked by the instruction stop (opcode 7fh). in stop mode, the operation of the cpu and all peripherals is halted. that is, the on-chip main oscillator stops and the supply current is reduced to less than 3 a. all system functions stop when the clock "freezes," but data stored in the internal register file is retained. stop mode can be released in one of two ways: by a reset or by interrupts. note do not use stop mode if you are using an external clock source because x in input must be restricted internally to v ss to reduce current leakage. using reset to release stop mode stop mode is released when the reset signal is released and returns to high level: all system and peripheral control registers are reset to their default hardware values and the contents of all data registers are retained. a reset operation automatically selects a slow clock (1/16) because clkcon.3 and clkcon.4 are cleared to '00b'. after the programmed oscillation stabilization interval has elapsed, the cpu starts the system initialization routine by fetching the program instruction stored in rom location 0100h (and 0101h). using an external interrupt to release stop mode external interrupts with an rc-delay noise filter circuit can be used to release stop mode. which interrupt you can use to release stop mode in a given situation depends on the microcontroller's current internal operating mode. the external interrupts in the s3c9484/c9488/f9488 interrupt structure that can be used to release stop mode are: ? external interrupts p3.3-p3.6 (int0-int3) please note the following conditions for stop mode release: ? if you release stop mode using an external interrupt, the current values in system and peripheral control registers are unchanged except stpcon register . ? if you use an external interrupt for stop mode release, you can also program the duration of the oscillation stabilization interval. to do this, you must make the appropriate control and clock settings before entering stop mode. ? when the stop mode is released by external interrupt, the clkcon.4 and clkcon.3 bit-pair setting remains unchanged and the currently selected clock value is used. ? the external interrupt is serviced when the stop mode release occurs. following the iret from the service routine, the instruction immediately following the one that initiated stop mode is executed. using an internal interrupt to release stop mode if you use watch timer with sub oscillator, stop mode is released by watch timer interrupt. how to enter into stop mode handling stpcon register then writing stop instruction. (keep the order)
s3c9484/c9488/f9488 reset and power-down 8- 5 attentions of using stop mode if you use 42-pin package, you must set p0.3- p0.4 for output mode and must set out value on low. and if you use 32-pin package, you must set p4.0- p4.6/p0.3- p0.7 for output mode and must set out value to low to prevent the leaky current in stop mode. idle mode idle mode is invoked by the instruction idle (opcode 6fh). in idle mode, cpu operations are halted while some peripherals remain active. during idle mode, the internal clock signal is gated away from the cpu, but all peripherals timers remain active. port pins retain the mode (input or output) they had at the time idle mode was entered. there are two ways to release idle mode: 1. execute a reset. all system and peripheral control registers are reset to their default values and the contents of all data registers are retained. the reset automatically selects the slow clock fxx/16 because clkcon.4 and clkcon.3 are cleared to ?00b?. if interrupts are masked, a reset is the only way to release idle mode. 2. activate any enabled interrupt, causing idle mode to be released. when you use an interrupt to release idle mode, the clkcon.4 and clkcon.3 register values remain unchanged, and the currently selected clock value is used. the interrupt is then serviced. when the return-from-interrupt (iret) occurs, the instruction immediately following the one that initiated idle mode is executed.
reset and power-down s3c9484 /c9488/f9488 8- 6 notes
s3c9484/c9488/f9488 i/o ports 9- 1 9 i/o ports overview the s3c9484/c9488/f9488 microcontroller has five bit-programmable i/o ports, p0-p4. the port 3 and 4 are 7-bit ports and the others are 8-bit ports. this gives a total of 38 i/o pins. each port can be flexibly configured to meet application design requirements. the cpu accesses ports by directly writing or reading port registers. no special i/o instructions are required. table 9-1 gives you a general overview of the s3c9484/c9488/f9488 i/o port functions. table 9-1. s3c9484/c9488/f9488 port configuration overview port configuration options 0 i/o port with bit-programmable pins. configurable to input or push-pull output mode. pull-up resistors can be assigned by software. pins can also be assigned individually as alternative function pins. 1 i/o port with bit-programmable pins. configurable to input or push-pull output mode. pull-up resistors can be assigned by software. pins can also be assigned individually as alternative function pins. 2 i/o port with bit-programmable pins. configurable to input mode, push-pull output mode. pins can also be assigned individually as alternative function pins. 3 i/o port with bit-programmable pins. configurable to input mode, push-pull output mode. pins can also be assigned individually as alternative function pins. 4 i/o port with bit-programmable pins. configurable to input mode, push-pull output mode. pins can also be assigned individually as alternative function pins.
i/o ports s3c9484/c 9488/f9488 9- 2 port data registers table 9-2 gives you an overview of the register locations of all five s3c9484/c9488/f9488 i/o port data registers. data registers for ports 0, 1, 2, 3, and 4 have the general format shown in figure 9-1. table 9-2. port data register summary register name mnemonic decimal hex r/w port 0 data register p0 224 e0h r/w port 1 data register p1 225 e1h r/w port 2 data register p2 226 e2h r/w port 3 data register p3 227 e3h r/w port 4 data register p4 228 e4h r/w
s3c9484/c9488/f9488 i/o ports 9- 3 port 0 port 0 is an 8-bit i/o port that you can use two ways: ? general-purpose i/o ? alternative function port 0 is accessed directly by writing or reading the port 0 data register, p0 at location e0h. port 0 control register (p0conh, p0conl, p0pur) port 0 pins are configured individually by bit-pair settings in three control registers located : p0conl (low byte, e7h) , p0conh (high byte, e6h) and p0pur (d2h). when you select output mode, a push-pull circuit is configured. in input mode, many different selections are available: ? input mode. ? push-pull output mode ? alternative function: lcd ?com? signal output ? com4, com5, com6, com7 ? alternative function: adc input mode ? adc4, adc5, adc6, adc7, adc8 ? alternative function: resetb ? alternative function: xtin/xtout
i/o ports s3c9484/c 9488/f9488 9- 4 port 0 control register, high byte (p0conh) e6h, r/w, reset value:00h lsb msb .7 .6 .5 .4 .3 .2 .1 .0 .5 .4 0 0 0 1 1 0 1 1 input mode alternative function: adc5 input push-pull output alternative function: lcd com5 signal output .3 .2 0 0 0 1 1 0 1 1 input mode alternative function: adc6 input push-pull output alternative function: lcd com6 signal output p0.6 com5/ adc5 p0.5 com6/ adc6 p0.7 com4/ adc4 p0.4 /com7 /adc7 .1 .0 0 0 0 1 1 0 1 1 input mode alternative function: adc7 input push-pull output alternative function: lcd com7 signal output .7 .6 0 0 0 1 1 0 1 1 input mode alternative function: adc4 input push-pull output alternative function: lcd com4 signal output note: you must be care of the pull-up resistor option. figure 9-1. port 0 high-byte control register (p0conh)
s3c9484/c9488/f9488 i/o ports 9- 5 port 0 control register, low byte (p0conl) e7h, r/w, reset value:00h lsb msb .7 .6 .5 .4 .3 .2 .1 .0 p0.3 /adc8 p0.2 p0.1 p0.0 .7 .6 0 x 1 0 1 1 input mode push-pull output alternative function: adc8 input .5 .4 0 x 1 x .3 .2 0 x 1 x .1 .0 0 x 1 x input mode push-pull output input mode push-pull output input mode push-pull output notes: 1. you must determine p0.0-p0.2 function on smart option. in other word, after reset operation, you cann't change p0.0-.2 function. if you selected normal i/o function at smart option, after reset operation, you can use on normal i/o and you can control p0.0-.2 by this control register value. 2. you must be care of the pull-up resistor option. figure 9-2. port 0 low-byte control register (p0conl)
i/o ports s3c9484/c 9488/f9488 9- 6 port 0 pull-up resistor control register (p0pur) d2h, r/w, reset value:ffh lsb msb .7 .6 .5 .4 .3 .2 .1 .0 0 1 pull-up resistor disable pull-up resistor enable p0.6 p0.1 p0pur pin configuration settings: p1.7 p1.5 p1.4 p1.3 p1.2 p1.0 figure 9-3. port 0 pull-up resistor control register (p0pur) port 1 port 1 is an 8-bit i/o port that you can use two ways: ? general-purpose i/o ? alternative function port 1 is accessed directly by writing or reading the port 1 data register, p1 at location e1h. port 1 control register (p1conh, p1conl, p1pur) port 1 pins are configured individually by bit-pair settings in three control registers located: p1conl(low byte, e9h), p1conh(high byte, e8h) and p1pur(d3h). when you select output mode, a push-pull circuit is configured. in input mode, many different selections are available: ? input mode. ? push-pull output mode ? alternative function: lcd ?com? signal output ? com0, com1, com2, com3 ? alternative function: tbpwm output ? alternative function: buz output ? alternative function: adc input mode ? adc0, adc1, adc2, adc3
s3c9484/c9488/f9488 i/o ports 9- 7 port 1 control register, high byte (p1conh) e8h, r/w, reset value:00h lsb msb .7 .6 .5 .4 .3 .2 .1 .0 .7 .6 0 x 1 0 1 1 input mode push-pull output alternative function: lcd com0 signal output .5 .4 0 x 1 0 1 1 .3 .2 0 x 1 0 1 1 .1 .0 0 x 1 0 1 1 input mode push-pull output alternative function: lcd com1 signal output input mode push-pull output alternative function: lcd com2 signal output input mode push-pull output alternative function: lcd com3signal output p1.7 /com0 p1.6 /com1 p1.5 /com2 p1.4 /com3 note: you must be care of the pull-up resistor option. figure 9-4. port 1 high-byte control register (p1conh)
i/o ports s3c9484/c 9488/f9488 9- 8 port 1 control register, low byte (p1conl) e9h, r/w, reset value:00h lsb msb .7 .6 .5 .4 .3 .2 .1 .0 .7 .6 0 x 1 0 1 1 input mode push-pull output alternative function: adc0 input .5 .4 0 x 1 0 1 1 .3 .2 0 0 0 1 1 0 1 1 .1 .0 0 0 0 1 1 0 1 1 input mode push-pull output alternative function: adc1 input input mode alternative function: buz output push-pull output alternative function: adc2 input input mode alternative function: tbpwm output push-pull output alternative function: adc3 input p1.3 /adc0 p1.2 /adc1 p1.1 /adc2 /buz p1.0 /adc3 /tbpwm note: you must be care of the pull-up resistor option. figure 9-5. port 1 low-byte control register (p1conl)
s3c9484/c9488/f9488 i/o ports 9- 9 port 1 pull-up resistor control register (p1pur) d3h, r/w, reset value:ffh lsb msb .7 .6 .5 .4 .3 .2 .1 .0 0 1 pull-up resistor disable pull-up resistor enable p1.7 p1.6 p1.5 p1.4 p1.3 p1.2 p1.1 p1.0 p1pur pin configuration settings: figure 9-6. port 1 pull-up resistor control register (p1pur)
i/o ports s3c9484/c 9488/f9488 9- 10 port 2 port 2 is an 8-bit i/o port that you can use two ways: ? general-purpose i/o ? alternative function port 2 is accessed directly by writing or reading the port 2 data register, p2 at location e2h. port 2 control register (p2conh, p2conl) port 2 pins are configured individually by bit-pair settings in two control registers located : p2conl (low byte, ebh) and p2conh (high byte, eah). when you select output mode, a push-pull circuit is configured. in input mode, many different selections are available: ? input mode ? push-pull output mode ? alternative function: lcd ?seg? signal output ? seg3, seg4, seg5, seg6, seg7, seg8, seg9, seg10 port 2 control register, low byte (p2conl) ebh, r/w, reset value:00h lsb msb .7 .6 .5 .4 .3 .2 .1 .0 p2.0/seg3 p2conl pin configuration settings: 00 01 10 11 input mode with pull-up input mode push-pull output alternative function: lcd seg(6-3) signal output p2.1/seg4 p2.2/seg5 p2.3/seg6 figure 9-7. port 2 high-byte c ontrol register (p2conh)
s3c9484/c9488/f9488 i/o ports 9- 11 port 2 control register, low byte (p2conl) ebh, r/w, reset value: 00h lsb msb .7 .6 .5 .4 .3 .2 .1 .0 p2.0/seg3 p2conl pin configuration settings: 0 0 0 1 1 0 1 1 input mode with pull-up input mode push-pull output alternative function: lcd seg(6-3) signal output p2.1/seg4 p2.2/seg5 p2.3/seg6 figure 9-8. port 2 low-byte control register (p2conl)
i/o ports s3c9484/c 9488/f9488 9- 12 port 3 port 3 is an 7-bit i/o port that you can use two ways: ? general-purpose i/o ? alternative function port 3 is accessed directly by writing or reading the port 3 data register, p3 at location e3h. port 3 control / interrupt control register (p3conh, p3conl) port 3 pins are configured individually by bit-pair settings in two control registers located: p3conl (low byte, edh) , p3conh (high byte, ech). when you select output mode, a push-pull circuit is configured. in input mode, many different selections are available: ? inpu t mode. ? push-pull output mode ? alternative function: timer a signal in/out mode ? taout(tapwm), tacap, tack ? alternative function: external interrupt input ? int0, int1, int2, int3 ? alternative function: lcd ?seg? signal output ? seg15, seg16, seg17, seg18 ? alternative function: uart module ? txd/rxd
s3c9484/c9488/f9488 i/o ports 9- 13 port 3 control register, high-byte (p3conh) ech, r/w, reset value:00h lsb msb .7 .6 .5 .4 .3 .2 .1 .0 .7 .6 0 0 0 1 1 0 1 1 input mode with pull-up; external interrupt input (int3); tacap input mode; external interrupt input (int3); tacap push-pull output open-drain output .5 .4 .3 .2 .1 .0 0 0 0 1 1 0 1 1 input mode with pull-up; external interrupt input (int1) input mode; external interrupt input (int1) push-pull output alternative mode; taout(tapwm) output p3.6 /tacap /int3 p3.5 /tack /int2 p3.4 /taout /int1 p3.3 /seg18 /int0 0 0 0 1 1 0 1 1 0 0 0 1 1 0 1 1 input mode with pull-up; external interrupt input (int2); tack input mode; external interrupt input (int2); tack push-pull output open-drain output input mode with pull-up; external interrupt input (int0) input mode; external interrupt input (int0) push-pull output alternative mode: lcd seg18 signal output note: reset value of p3conh is determined by smart option 3dh . figure 9-9. port 3 high-byte control register (p3conh)
i/o ports s3c9484/c 9488/f9488 9- 14 port 3 control register, low byte (p3conl) edh, r/w, reset value:00h lsb msb .7 .6 .5 .4 .3 .2 .1 .0 .7 .6 .5 0 0 0 0 0 1 0 1 0 0 1 1 1 x x input mode with pull-up input mode push-pull output alternative mode; txd output alternative mode; lcd seg17 signal output .4 .3 .2 .1 .0 input mode with pull-up input mode push-pull output alternative mode; lcd seg15 signal output p3.2/seg17/txd p3.1/seg16/rxd p3.0/seg15 0 0 0 0 0 1 0 1 0 0 1 1 1 x x 0 0 0 1 1 0 1 1 input mode with pull-up; rxd input input mode; rxd input push-pull output alternative mode: rxd output alternative mode: lcd seg16 signal output figure 9-10. port 3 low-byte control register (p3conl)
s3c9484/c9488/f9488 i/o ports 9- 15 port 3 interrupt control register (p3int) eeh, r/w, reset value:00h lsb msb .7 .6 .5 .4 .3 .2 .1 .0 int3 interrupt enable/disable selection 0 x 1 0 1 1 interrupt disable interrupt enable; falling edge interrupt enable; rising edge int2 int1 int0 figure 9-12. port 3 interrupt control register (p3int) port 3 interrupt pending register (p3pnd) efh, r/w, reset value:00h lsb msb .7 .6 .5 .4 .3 .2 .1 .0 int3 pending bit: 0 1 no interrupt pending (when write, pending clear) interrupt is pending int2 int1 int0 not used figure 9-13. port 3 interrupt pending register (p3pnd)
i/o ports s3c9484/c 9488/f9488 9- 16 port 4 port 4 is an 7-bit i/o port with individually configurable pins. port 4 pins are accessed directly by writing or reading the port 4 data register, p4 at location e4h. p4.0-p4.6 can serve as inputs (with or without pull-up), and push-pull output. and they can serve as segment pins for lcd. port 4 control register (p4conh, p4conl) port 4 pins are configured individually by bit-pair settings in two control registers located : p4conl (low byte, f1h) , p4conh (high byte, f0h) when you select output mode, a push-pull circuit is configured. in input mode, many different selections are available: ? input mode. ? push-pull output mode ? alternative function: lcd ?seg? signal output ? seg0, seg1, seg2, seg11, seg12, seg13, seg14 port 4 control register, high-byte (p4conh) f0h, r/w, reset value:00h lsb msb .7 .6 .5 .4 .3 .2 .1 .0 p4.4/seg12 .5 .4 .3 .2 .1 .0 p4.5/seg13 p4.6/seg14 not used 0 0 0 1 1 0 1 1 input mode with pull-up input mode push-pull output alternative mode: lcd seg14 signal output 0 0 0 1 1 0 1 1 input mode with pull-up input mode push-pull output alternative mode: lcd seg13 signal output 0 0 0 1 1 0 1 1 input mode with pull-up input mode push-pull output alternative mode: lcd seg12 signal output figure 9-14. port 4 high-byte control register (p4conh)
s3c9484/c9488/f9488 i/o ports 9- 17 port 4 control register, low-byte (p4conl) f1h, r/w, reset value:00h lsb msb .7 .6 .5 .4 .3 .2 .1 .0 p4.0/seg0 .7 .6 0 0 0 1 1 0 1 1 input mode with pull-up input mode push-pull output alternative mode: lcd seg11 signal output .5 .4 .3 .2 .1 .0 p4.1/seg1 p4.2/seg2 p4.3/seg11 0 0 0 1 1 0 1 1 input mode with pull-up input mode push-pull output alternative mode: lcd seg2 signal output 0 0 0 1 1 0 1 1 input mode with pull-up input mode push-pull output alternative mode: lcd seg1 signal output 0 0 0 1 1 0 1 1 input mode with pull-up input mode push-pull output alternative mode: lcd seg0 signal output figure 9-15. port 4 low-byte control register (p4conl)
i/o ports s3c9484/c 9488/f9488 9- 18 notes
s3c9484/c9488/f9488 basic timer 10- 1 10 basic timer overview basic timer (bt) you can use the basic timer (bt): ? to signal the end of the required oscillation stabilization interval after a reset or a stop mode release. the functional components of the basic timer block are: ? clock frequ ency divider (fxx divided by 4096, 1024 or 128) with multiplexer ? 8-bit basic timer counter, btcnt (ddh, read-only) ? basic timer control register, btcon (dch, read/write) basic timer control register (btcon) the basic timer control register, btcon, is used to select the input clock frequency, to clear the basic timer counter and frequency dividers. it is located in address dch, and is read/write addressable using register addressing mode. a reset clears btcon to '00h'. this enables selects a basic timer clock frequency of f xx /4096. the 8-bit basic timer counter, btcnt (ddh), can be cleared at any time during normal operation by writing a "1" to btcon.1. to clear the frequency dividers, write a "1" to btcon.0.
basic timer s3c9484 /c9488/f9488 10- 2 basic timer control register (btcon) dch, r/w, reset value:00h lsb msb .7 .6 .5 .4 .3 .2 .1 .0 divider clear bit: 0 = no effect 1 = clear divider basic timer counter clear bit: 0 = no effect 1 = clear btcnt basic timer input clock selection bit: 00 = fxx/4096 01 = fxx/1024 10 = fxx/128 11 = not used not used figure 10-1. basic timer control register (btcon)
s3c9484/c9488/f9488 basic timer 10- 3 basic timer function description oscillation stabilization interval timer function you can also use the basic timer to program a specific oscillation stabilization interval following a reset or when stop mode has been released by an external interrupt. in stop mode, whenever a reset or an external interrupt occurs, the oscillator starts. the btcnt value then starts increasing at the rate of fxx/4096 (for reset), or at the rate of the preset clock source (for an external interrupt). when btcnt.4 overflows, a signal is generated to indicate that the stabilization interval has elapsed and to gate the clock signal off to the cpu so that it can resume normal operation. in summary, the following events occur when stop mode is released: 1. during stop mode, a power-on reset or an interrupt occurs to trigger the stop mode release and oscillation starts. 2. if a power-on reset occurred, the basic timer counter will increase at the rate of f xx /4096. if an interrupt is used to release stop mode, the btcnt value increases at the rate of the preset clock source. 3. clock oscillation stabilization interval begins and continues until bit 4 of the basic timer counter overflows. 4. when a btcnt.4 overflow occurs, normal cpu operation resumes. note: during a power-on reset operation, the cpu is idle during the required oscillation stabilization interval (until bit 4 of the basic timer counter overflows). mux f xx/4096 div f xx/1024 f xx/128 fxx bits 3, 2 bit 0 clear bit 1 reset or stop data bus 8-bit up counter (btcnt, read-only) start the cpu (note) r figure 10-2. basic timer block diagram
basic timer s3c9484 /c9488/f9488 10- 4 notes
s3c9484/c9488/f9488 8-bit timer a/b 11- 1 11 8-bit timer a/b 8-bit timer a overview the 8-bit timer a is an 8-bit general-purpose timer/counter. timer a has three operating modes, you can select one of them using the appropriate tacon setting: ? interval timer mode (toggle output at taout pin) ? capture input mode with a rising or falling edge trigger at the tacap pin ? pwm mode (taout) timer a has the following functional components: ? clock frequency divider (fxx divided by 1024, 256, or 64) with multiplexer ? external clock input pin (tack) ? 8-bit counter (tacnt), 8-bit comparator, and 8-bit reference data register (tadata) ? i/o pins for capture input (tacap) or pwm or match output (taout) ? timer a overflow interrupt and match/capture i nterrupt generation ? timer a control register, tacon (f3h, read/write)
8-bit timer a/b s3c 9484/c9488/f9488 11- 2 function description timer a interrupts the timer a module can generate two interrupts: the timer a overflow interrupt (taovf), and the timer a match/ capture interrupt (taint). timer a overflow interrupt pending condition must be cleared by software when it has been serviced. timer a match/capture interrupt, taint pending condition is also cleared by software when it has been serviced. interval timer function the timer a module can generate an interrupt: the timer a match interrupt (taint). when timer a interrupt occurs and is serviced by the cpu, the pending condition have to be cleared by software. in interval timer mode, a match signal is generated and taout is toggled when the counter value is identical to the value written to the ta reference data register, tadata. the match signal generates a timer a match interrupt and clears the counter. if, for example, you write the value 10h to tadata and 0ah to tacon, the counter will increment until it reaches 10h. at this point, the ta interrupt request is generated, the counter value is reset, and counting resumes. pulse width modulation mode pulse width modulation (pwm) mode lets you program the width (duration) of the pulse that is output at the taout pin. as in interval timer mode, a match signal is generated when the counter value is identical to the value written to the timer a data register. in pwm mode, however, the match signal does not clear the counter. instead, it runs continuously, overflowing at ffh, and then continues incrementing from 00h. although you can use the match signal to generate a timer a overflow interrupt, interrupts are not typically used in pwm-type applications. instead, the pulse at the taout pin is held to low level as long as the reference data value is less than or equal to ( ) the counter value and then the pulse is held to high level for as long as the data value is greater than ( > ) the counter value. one pulse width is equal to t clk ? 256 . capture mode in capture mode, a signal edge that is detected at the tacap pin opens a gate and loads the current counter value into the tadata register. you can select rising or falling edges to trigger this operation. timer a also gives you capture input source: the signal edge at the tacap pin. you select the capture input by setting the value of the timer a capture input selection bit in the port 3 high?byte control register, p3conh, (ech). when p3conh.5.4 is 00 and 01, the tacap input or normal input is selected. when p3conh.5.4 is set to 10 and 11, output is selected. both kinds of timer a interrupts can be used in capture mode: the timer a overflow interrupt is generated whenever a counter overflow occurs; the timer a match/capture interrupt is generated whenever the counter value is loaded into the tadata register. by reading the captured data value in tadata, and assuming a specific value for the timer a clock frequency, you can calculate the pulse width (duration) of the signal that is being input at the tacap pin.
s3c9484/c9488/f9488 8-bit timer a/b 11- 3 timer a control register (tacon) you use the timer a control register, tacon ? select the timer a operating mode (interval timer, capture mode and pwm mode) ? select the timer a input clock frequency ? clear the timer a counter, tacnt ? enable the timer a overflow interrupt or timer a match/capture interrupt ? timer a start/stop ? clear timer a match/capture interrupt pending conditions tacon is located at address f3h, and is read/write addressable using register addressing mode. a reset clears tacon to '00h'. this sets timer a to normal interval timer mode, selects an input clock frequency of fxx/1024, and disables all timer a interrupts. you can clear the timer a counter at any time during normal operation by writing a "1" to tacon.3. you can start the timer a counter by writing a ?1? to tacon.0. the timer a overflow interrupt (taovf) has the vector address 00h-01h. when a timer a overflow interrupt occurs and is serviced by the cpu, but the pending condition must clear by software. to enable the timer a match/capture interrupt , you must write tacon.1 to "1". to generate the exact time interval, you should write tacon.3 and .0, which cleared counter and interrupt pending bit. when interrupt service routine is served, the pending condition must be cleared by software by writing a ?0? to the interrupt pending bit. timer a control register (tacon) f3h, r/w, reset: 00h lsb msb .7 .6 .5 .4 .3 .2 .1 .0 timer a match/capture interrupt enable bit: 0 = disable interrupt 1 = enable interrrupt timer a input clock selection bit: 00 = fxx/1024 01 = fxx/256 10 = fxx/64 11 = external clock (tack) timer a operating mode selection bit: 00 = interval mode (taout mode) 01 = capture mode (capture on rising edge, counter running, ovf can occur) 10 = capture mode (capture on falling edge, counter running, ovf can occur) 11 = pwm mode (ovf interrupt and match interrupt can occur) timer a start/stop bit: 0 = stop timer a 1 = start timer a timer a overflow interrupt enable bit: 0 = disable overflow interrupt 1 = enable overflow interrrupt timer a counter clear bit: 0 = no effect 1 = clear the timer a counter ( when write ) note: when th counter clear bit(.3) is set, the 8-bit counter is cleared and it also is cleared automatically. figure 11-1. timer a control register (tacon)
8-bit timer a/b s3c 9484/c9488/f9488 11- 4 timer interrupt pending register (tintpnd) f2h, reset: 00h, r/w not used timer a macth/capture interrupt pending flag: 0 = not pending 0 = clear pending bit (when write) 1 = interrupt pending timer a overflow interrupt pending flag: 0 = not pending 0 = clear pending bit (when write) 1 = interrupt pending timer b underflow interrupt pending flag: 0 = not pending 0 = clear pending bit (when write) 1 = interrupt pending .7 msb lsb .6 .5 .4 .3 .2 .1 .0 figure 11-2. timer interrupts pending register (tintpnd) timer a data register (tadata) f5h, r/w .7 msb lsb .6 .5 .4 .3 .2 .1 .0 reset value: ffh figure 11-3. timer a data register (tadata)
s3c9484/c9488/f9488 8-bit timer a/b 11- 5 block diagram notes: 1. when pwm mode, match signal cannot clear counter. 2. pending bit is located at tintpnd register. clear match tacon.2 pending tacon.3 overflow taovf tacap tintpnd.0 tacon.5.4 tacon.5.4 data bus 8 data bus 8 m u x 8-bit up-counter (read only) 8-bit comparator timer a buffer reg timer a data register (read/write) m u x tacon.1 pending taint tintpnd.1 tacon.0 tacon.7-.6 f xx/1024 f xx/256 f xx/64 tack m u x taout m u x figure 11-4. timer a functional block diagram
8-bit timer a/b s3c 9484/c9488/f9488 11- 6 8-bit timer b overview the s3c9484/c9488/f9488 micro-controller has an 8-bit counter called timer b. timer b, which can be used to generate the carrier frequency of a remote controller signal. as a normal interval timer, generating a timer b interrupt at programmed time intervals. tbcon.6-.7 f xx/1 data bus note: in case of setting tbcon.5-.4 at '10', the value of the tbdatal register is loaded into the 8-bit counter when the operation of the timer b starts. and then if a underflow occurs in the counter, the value of the tbdatah register is loaded with the value of the 8-bit counter. however, if the next borrow occurs, the value of the tbdatal register is loaded with the value of the 8-bit counter. m u x f xx/2 f xx/4 f xx/8 tbcon.2 clk 8-bit down counter mux timer b data low byte register timer b data high byte register repeat control tbcon.0 t-ff tbcon.4-.5 tbcon.3 tb underflow (tbuf) tbint tbpwm pending tintpnd.2 figure 11-5. timer b functional block diagram
s3c9484/c9488/f9488 8-bit timer a/b 11- 7 timer b control register (tbcon) f8h, r/w, reset: 00h lsb msb .7 .6 .5 .4 .3 .2 .1 .0 timer b mode selection bit: 0 = one-shot mode 1 = repeating mode timer b input clock selection bit: 00 = fxx/1 01 = fxx/2 10 = fxx/4 11 = fxx/8 timer b interrupt time selection bit: 00 = interrupt on tbdatal underflow 01 = interrupt on tbdatah underflow 10 = interrupt on tbdatah and tbdatal underflow 11 = invaild setting timer b start/stop bit: 0 = stop timer b 1 = start timer b timer b underflow interrupt enable bit: 0 = disable interrupt 1 = enable interrupt timer b output flip-flop control bit: 0 = t-ff is low 1 = t-ff is high figure 11-6. timer b control register (tbcon) timer b data high-byte register (tbdatah) f6h, r/w lsb msb .7 .6 .5 .4 .3 .2 .1 .0 reset value: ffh timer b data low-byte register (tbdatal) f7h, r/w lsb msb .7 .6 .5 .4 .3 .2 .1 .0 reset value: ffh figure 11-7. timer b data registers (tbdatah, tbdatal)
8-bit timer a/b s3c 9484/c9488/f9488 11- 8 + programming tip ? using timer a (fxx ? 8mhz, 800 m sec interval) .include "c:\skstudio\include\reg\s3c9488.reg" vector 00h,f9488_int .org 003ch db 0ffh db 0ffh db 01100000b ;disable lvr db 00000011b ;sub oscil lator,bt overflow, reset pin enalbe .org 100h reset: di ld wdtcon,#10101010b ld btcon,#0001011b ld clkcon,#00011000b ld sp,#0c0h ld sym,#00h ld osccon,#00000000b ld p3conh,#10101110b ;taout ld tadata,#100 ld tacon,#10001011b ;fxx/64,interval mode,timer start. ei ;================================================================================ main jp main ;================================================================================ f9488_int tm tintpnd,#01h ;check what interrupt is enabled jp nc,ta_mc_int ;.......... iret ta_mc_int ld tintpnd,#0 nop nop iret .end
s3c9484/c9488/f9488 8-bit timer a/b 11- 9 + programming tip ? using timer b (fxx ? 8mhz, duty ? 2:8, 80khz) .include "c:\skstudio\include\reg\s3c9488.reg" vector 00h,f9488_int .org 003ch db 0ffh db 0ffh db 01100000b ;disable lvr db 00000011b ;sub oscillator,bt overflow, reset pin enalbe .org 100h reset: di ld wdtcon,#10101010b ld btcon,#0001011b ld cl kcon,#00011000b ld sp,#0c0h ld sym,#00h ld osccon,#00000000b ld p1conl,#10101001b ;tb pwm ld tbdatah,#79 ld tbdatal,#19 ld tbcon,#00101111b ;fxx,repeat mode,flip-flop high,timer start. ei ;================================================================================ main jp main ;================================================================================ f9488_int tm tintpnd,#04h ;check what interrupt is enabled jp nc,tb_uf_int ;.......... iret tb_uf_int ld tintpnd,#0 nop nop iret .end
8-bit timer a/b s3c 9484/c9488/f9488 11- 10 notes
s3c9484/c9488/f9488 uart 12- 1 12 uart overview the uart block has a full-duplex serial port with programmable operating modes: there is one synchronous mode and three uart (universal asynchronous receiver/transmitter) modes: ? shift register i/o with baud rate of fxx/(16 (16bit brdata+1)) ? 8-bit uart mode; variable baud rate, fxx/(16 (16bit brdata+1)) ? 9-bit uart mode; variable baud rate, fxx/(16 (16bit brdata+1)) uart receive and transmit buffers are both accessed via the data register, udata, is at address ffh. writing to the uart data register loads the transmit buffer; reading the uart data register accesses a physically separate receive buffer. when accessing a receive data buffer (shift register), reception of the next byte can begin before the previously received byte has been read from the receive register. however, if the first byte has not been read by the time the next byte has been completely received, the first data byte will be lost (overrun error). in all operating modes, transmission is started when any instruction (usually a write operation) uses the udata register as its destination address. in mode 0, serial data reception starts when the receive interrupt pending bit (uartpnd.1) is "0" and the receive enable bit (uartcon.4) is "1". in mode 1 and 2, reception starts whenever an incoming start bit ("0") is received and the receive enable bit (uartcon.4) is set to "1". programming procedure to program the uart modules, follow these basic steps: 1. configure p3.1 and p3.2 to alternative function (rxd (p3.1), txd (p3.2)) for uart module by setting the p3conl register to appropriate value. 2. load an 8-bit value to the uartcon control register to properly configure the uart i/o module. 3. for parity generation and check in uart mode 2, set parity enable bit (uartpnd.5) to ?1?. 4. for interrupt generation, set the uart interrupt enable bit (uartcon.1 or uartcon.0) to "1". 5. when you transmit data to the uart buffer, write transmit data to udata, the shift operation starts. 6. when the shift operation (transmit/receive) is completed, uart pending bit (uartpnd.1 or uartpnd.0) is set to "1" and an uart interrupt request is generated.
uart s3c9484/c9488/ f9488 12- 2 uart control register (uartcon) the control register for the uart is called uartcon at address fdh. it has the following control functions: ? operating mode and baud rate selection ? multiprocessor communication and interrupt control ? serial receive enable/disable control ? 9th data bit location for transmit and receive operations (mode 2) ? parity generation and check for transmit and receive operations (mode 2) ? uart transmit and receive interrupt control a reset clears the uartcon value to "00h". so, if you want to use uart module, you must write appropriate value to uartcon.
s3c9484/c9488/f9488 uart 12- 3 if parity disable mode (pen = 0), location of the 9th data bit that was received in uart mode 2 ("0" or "1"). if parity enable mode (pen = 1), even/odd parity selection bit for receive data in uart mode 2. 0: even parity check for the received data 1: odd parity check for the received data uart control register (uartcon) fdh, r/w, reset value: 00h ms1 msb lsb received interrupt enable bit: 0 = disable 1 = enable transmit interrupt enable bit: 0 = disable 1 = enable serial data receive enable bit: 0 = disable 1 = enable multiprocessor communication enable bit (mode 2 only): (1) 0 = disable 1 = enable if parity disable mode (pen = 0), location of the 9th data bit to be transmitted in uart mode 2 ("0" or "1"). if parity enable mode (pen = 1), even/odd parity selection bit for transmit data in uart mode 2; 0: even parity bit generation for transmit data 1: odd parity bit generation for transmit data operating mode and baud rate selection bits (see table below) ms0 mce re tb8 rb8 rie tie ms1 ms0 0 0 1 0 1 x description baud rate 0 1 2 shift register 8-bit uart 9-bit uart fxx / (16 x (16bit brdata + 1)) fxx / (16 x (16bit brdata + 1)) fxx / (16 x (16bit brdata + 1)) notes: 1. in mode 2, if the uartcon.5 bit is set to "1" then the receive interrupt will not be activated if the received 9th data bit is "0". in mode 1, if uartcon.5 = "1" then the receive interrut will not be activated if a valid stop bit was not received. 2. the descriptions for 8-bit and 9-bit uart mode do not include start and stop bits of serial data for receiving and transmitting. 3. parity enable bits, pen, is located in the uartpnd register at address feh. 4. parity enable and parity error check can be available in 9-bit uart mode (mode 2) only. mode figure 12-1. uart control register (uartcon)
uart s3c9484/c9488/ f9488 12- 4 uart interrupt pending register (uartpnd) the uart interrupt pending register, uartpnd is located at address feh. it contains the uart data transmit interrupt pending bit (uartpnd.0) and the receive interrupt pending bit (uartpnd.1). in mode 0 of the uart module, the receive interrupt pending flag uartpnd.1 is set to "1" when the 8th receive data bit has been shifted. in mode 1 or 2, the uartpnd.1 bit is set to "1" at the halfway point of the stop bit's shift time. when the cpu has acknowledged the receive interrupt pending condition, the uartpnd.1 flag must be cleared by software in the interrupt service routine. in mode 0 of the uart module, the transmit interrupt pending flag uartpnd.0 is set to "1" when the 8th transmit data bit has been shifted. in mode 1 or 2, the uartpnd.0 bit is set at the start of the stop bit. when the cpu has acknowledged the transmit interrupt pending condition, the uartpnd.0 flag must be cleared by software in the interrupt service routine. uart pending register (uartpnd) feh, r/w, reset value: 00h .7 msb lsb uart receive interrupt pending flag: 0 = not pending 0 = clear pending bit (when write) 1 = interrupt pending uart transmit interrupt pending flag: 0 = not pending 0 = clear pending bit (when write) 1 = interrupt pending uart receive parity error: 0 = no error 1 = parity error uart parity enable/disable: 0 = disable 1 = enable not used .6 pen rpe .3 .2 rip tip notes: 1. in order to clear a data transmit or receive interrupt pending flag, you must write a "0" to the appropriate pending bit. a "0" has no effect. 2. to avoid errors, we recommended using load instruction, when manipulating uartpnd value. 3. parity enable and parity error check can be available in 9-bit uart mode (mode 2) only. 4. parity error bit (rpe) will be refreshed whenever 8th receive data bit has been shifted. not used figure 12-2. uart interrupt pending register (uartpnd)
s3c9484/c9488/f9488 uart 12- 5 in mode 2 (9-bit uart data), by setting the parity enable bit (pen) of uartpnd register to '1', the 9 th data bit of transmit data will be an automatically generated parity bit. also, the 9 th data bit of the received data will be treated as a parity bit for checking the received data. in parity enable mode (pen = 1), uartcon.3 (tb8) and uartcon.2 (rb8) will be a parity selection bit for transmit and receive data respectively. the uartcon.3 (tb8) is for settings of the even parity generation (tb8 = 0) or the odd parity generation (tb8 = 0) in the transmit mode. the uartcon.2 (rb8) is also for settings of the even parity checking (rb8= 0) or the odd parity checking (rb8 =1) in the receive mode. the parity enable (generation/checking) functions are not available in uart mode 0 and 1. if you don?t want to use a parity mode, uartcon.2 (rb8) and uartcon.3 (tb8) are a normal control bit as the 9 th data bit, in this case, pen must be disable (?0?) in mode 2. also it is needed to select the 9th data bit to be transmitted by writing tb8 to "0" or "1". the receive parity error flag (rpe) will be set to ?0? or ?1? depending on parity error whenever the 8 th data bit of the receive data has been shifted. uart data register (udata) uart data register (udata) ffh, r/w, reset value: undefined .7 msb lsb transmit or receive data .6 .5 .4 .3 .2 .1 .0 figure 12-3. uart data register (udata)
uart s3c9484/c9488/ f9488 12- 6 uart baud rate data register (brdatah, brdatal) the value stored in the uart baud rate register, (brdatah, brdatal), lets you determine the uart clock rate (baud rate). uart baud rate data register (brdatah) dah, r/w, reset value: ffh (brdatal) dbh, r/w, reset value: ffh .7 msb lsb .6 .5 .4 .3 .2 .1 .0 baud rate data figure 12-4. uart baud rate data register (brdatah, brdatal) baud rate calculations the baud rate is determined by the baud rate data register, 16bit brdata mode 0 baud rate = fxx/(16 (16bit brdata + 1)) mode 1 baud rate = fxx/(16 (16bit brdata + 1)) mode 2 baud rate = fxx/(16 (16bit brdata + 1))
s3c9484/c9488/f9488 uart 12- 7 table 12-1. commonly used baud rates generated by 16-bit brdata baud rate oscillation clock brdatah brdatal decimal hex decimal hex 230,400 hz 11.0592 mhz 0 0h 02 02h 115,200 hz 11.0592 mhz 0 0h 05 05h 57,600 hz 11.0592 mhz 0 0h 11 0bh 38,400 hz 11.0592 mhz 0 0h 17 11h 19,200 hz 11.0592 mhz 0 0h 35 23h 9,600 hz 11.0592 mhz 0 0h 71 47h 4,800 hz 11.0592 mhz 0 0h 143 8fh 76,800 hz 10 mhz 0 0h 7 7h 38,400 hz 10 mhz 0 0h 15 fh 19,200 hz 10 mhz 0 0h 31 1fh 9,600 hz 10 mhz 0 0h 64 40h 4,800 hz 10 mhz 0 0h 129 81h 2,400 hz 10 mhz 1 1h 3 3h 600 hz 10 mhz 4 4h 16 10h 38,461 hz 8 mhz 0 0h 12 0ch 12,500 hz 8 mhz 0 0h 39 27h 19,230 hz 4 mhz 0 0h 12 0ch 9,615 hz 4 mhz 0 0h 25 19h
uart s3c9484/c9488/ f9488 12- 8 block diagram zero detector udata rxd (p3.1) tie rie interrupt 1-to-0 transition detector re rie bit detector shift value ms0 ms1 ms0 ms1 rxd (p3.1) sam88 internal data bus write to udata baud rate generator s d q clk tb8 clk tx control start tx clock tip shift en send rx control rx clock start rip receive shift shift clock ms0 ms1 fxx sam88 internal data bus shift register udata 16 bit brdata txd (p3.2) txd (p3.2) figure 12-5. uart functional block diagram
s3c9484/c9488/f9488 uart 12- 9 uart mode 0 function description in mode 0, uart is input and output through the rxd (p3.1) pin and txd (p3.2) pin outputs the shift clock. data is transmitted or received in 8-bit units only. the lsb of the 8-bit value is transmitted (or received) first. mode 0 transmit procedure 1. select mode 0 by setting uartcon.6 and .7 to "00b". 2. write transmission data to the shift register udata (ffh) to start the transmission operation. mode 0 receive procedure 1. select mode 0 by setting uatcon.6 and .7 to "00b". 2. clear the receive interrupt pending bit (uartpnd.1) by writing a "0" to uartpnd.1. 3. set the uart receive enable bit (uartcon.4) to "1". 4. the shift clock will now be output to the txd (p3.2) pin and will read the data at the rxd (p3.1) pin. a uart receive interrupt (vector 00h-01h) occurs when uartcon.1 is set to "1". transmit d0 d1 d2 d3 d4 d5 d6 d7 write to shift register (udata) rxd (data out) txd (shift clock) tip shift receive write to uartpnd (clear rip and set re) shift d0 d1 d2 d3 d4 d5 d6 d7 txd (shift clock) rxd (data in) re rip 1 2 3 4 5 6 7 8 figure 12-6. timing diagram for uart mode 0 operation
uart s3c9484/c9488/ f9488 12- 10 uart mode 1 function description in mode 1, 10-bits are transmitted (through the txd (p3.2) pin) or received (through the rxd (p3.1) pin). each data frame has three components: ? start bit ("0") ? 8 data bits (lsb first) ? stop bit ("1") when receiving, the stop bit is written to the rb8 bit in the uartcon register. the baud rate for mode 1 is variable. mode 1 transmit procedure 1. select the baud rate generated by 16bit brdata. 2. select mode 1 (8-bit uart) by setting uartcon bits 7 and 6 to ' 01b'. 3. write transmission data to the shift register udata (ffh). the start and stop bits are generated automatically by hardware. mode 1 receive procedure 1. select the baud rate to be generated by 16bit brdata. 2. select mode 1 and set the re (receive enable) bit in the uartcon register to "1". 3. the start bit low ("0") condition at the rxd (p3.1) pin will cause the uart module to start the serial data receive operation. transmit tip write to shift register (udata) start bit txd stop bit d0 d1 d2 d3 d4 d5 d6 d7 shift tx clock receive rip start bit rx clock stop bit rxd d0 d1 d2 d3 d4 d5 d6 d7 bit detect sample time shift figure 12-7. timing diagram for uart mode 1 operation
s3c9484/c9488/f9488 uart 12- 11 uart mode 2 function description in mode 2, 11-bits are transmitted (through the txd pin) or received (through the rxd pin). each data frame has four components: ? start bit ("0") ? 8 data bits (lsb first) ? programmable 9th data bit or parity bit ? stop bit ("1") < in parity disable mode (pen = 0) > the 9th data bit to be transmitted can be assigned a value of "0" or "1" by writing the tb8 bit (uartcon.3). when receiving, the 9th data bit that is received is written to the rb8 bit (uartcon.2), while the stop bit is ignored. the baud rate for mode 2 is fosc/(16 x (16bit brdata + 1)) clock frequency. < in parity enable mode (pen = 1) > the 9th data bit to be transmitted can be an automatically generated parity of "0" or "1" depending on a parity generation by means of tb8 bit (uartcon.3). when receiving, the received 9th data bit is treated as a parity for checking receive data by means of the rb8 bit (uartcon.2), while the stop bit is ignored. the baud rate for mode 2 is fosc/(16 (16bit brdata + 1)) clock frequency. mode 2 transmit procedure 1. select the baud rate generated by 16bit brdata. 2. select mode 2 (9-bit uart) by setting uartcon bits 6 and 7 to '10b'. also, select the 9th data bit to be transmitted by writing tb8 to "0" or "1" and set pen bit of uartpnd register to ?0? if you don?t use a parity mode. if you want to use the parity enable mode, select the parity bit to be transmitted by writing tb8 to "0" or "1" and set pen bit of uartpnd register to ?1?. 3. write transmission data to the shift register, udata (ffh), to start the transmit operation. mode 2 receive procedure 1. select the baud rate to be generated by 16bit brdata. 2. select mode 2 and set the receive enable bit (re) in the uartcon register to "1". 3. if you don?t use a parity mode, set pen bit of uartpnd register to ?0? to disable parity mode. if you want to use the parity enable mode, select the parity type to be check by writing tb8 to "0" or "1" and set pen bit of uartpnd register to ?1?. only 8 bits (bit0 to bit7) of received data are available for data value. 4. the receive operation starts when the signal at the rxd pin goes to low level.
uart s3c9484/c9488/ f9488 12- 12 transmit tip write to shift register (uartdata) start bit txd stop bit d0 d1 d2 d3 d4 d5 d6 d7 shift tx clock receive rip start bit rx clock stop bit rxd d0 d1 d2 d3 d4 d5 d6 d7 bit detect sample time shift tb8 or parity bit rb8 or parity bit figure 12-8. timing diagram for uart mode 2 operation
s3c9484/c9488/f9488 uart 12- 13 serial communication for multiprocessor configurations the s3c9-series multiprocessor communication features let a "master" s3c9484/c9488/f9488 send a multiple- frame serial message to a "slave" device in a multi- s3c9484/c9488/f9488 configuration. it does this without interrupting other slave devices that may be on the same serial line. this feature can be used only in uart mode 2 with the parity disable mode. in mode 2, 9 data bits are received. the 9th bit value is written to rb8 (uartcon.2). the data receive operation is concluded with a stop bit. you can program this function so that when the stop bit is received, the serial interrupt will be generated only if rb8 = "1". to enable this feature, you set the mce bit in the uartcon registers. when the mce bit is "1", serial data frames that are received with the 9th bit = "0" do not generate an interrupt. in this case, the 9th bit simply separates the address from the serial data. sample protocol for master/slave interaction when the master device wants to transmit a block of data to one of several slaves on a serial line, it first sends out an address byte to identify the target slave. note that in this case, an address byte differs from a data byte: in an address byte, the 9th bit is "1" and in a data byte, it is "0". the address byte interrupts all slaves so that each slave can examine the received byte and see if it is being addressed. the addressed slave then clears its mce bit and prepares to receive incoming data bytes. the mce bits of slaves that were not addressed remain set, and they continue operating normally while ignoring the incoming data bytes. while the mce bit setting has no effect in mode 0, it can be used in mode 1 to check the validity of the stop bit. for mode 1 reception, if mce is "1", the receive interrupt will be issue unless a valid stop bit is received.
uart s3c9484/c9488/ f9488 12- 14 setup procedure for multiprocessor communications follow these steps to configure multiprocessor communications: 1. set all s3c9484/c9488/f9488 devices (masters and sl aves) to uart mode 2 with parity disable. 2. write the mce bit of all the slave devices to "1". 3. the master device's transmission protocol is: ? first byte: the address identifying the target slave device (9th bit = "1") ? next bytes: data (9th bit = "0") 4. when the target slave receives the first byte, all of the slaves are interrupted because the 9th data bit is "1". the targeted slave compares the address byte to its own address and then clears its mce bit in order to receive incoming data. the other slaves continue operating normally. full-duplex multi-s3c9484/c9488/f9488 interconnect . . . txd rxd master s3c9484/ c9488/ f9488 txd rxd slave 1 txd rxd slave 2 txd rxd slave n s3c9484/ c9488/ f9488 s3c9484/ c9488/ f9488 s3c9484/ c9488/ f9488 figure 12-9. connection example for multiprocessor serial data communications
s3c9484/c9488/f9488 watch timer 13- 1 13 watch timer overview watch timer functions include real-time and watch-time measurement and interval timing for the system clock. to start watch timer operation, set bit 1 and bit 6 of the watch timer mode register, wtcon.1 and .6, to "1". after the watch timer starts and elapses a time, the watch timer interrupt is automatically set to "1", and interrupt requests commence in 3.9ms, 0.25 s, 0.5s or 1.0s intervals. the watch timer can generate a steady 0.5khz, 1khz, 2 khz or 4 khz signal to the buzzer output. by setting wtcon.3 and wtcon.2 to "11b", the watch timer will function in high-speed mode, generating an interrupt every 3.91 ms. high-speed mode is useful for timing events for program debugging sequences. the watch timer supplies the clock frequency for the lcd controller (f lcd ). therefore, if the watch timer is disabled, the lcd controller does not operate . ? real-time and watch-time measurement ? using a main system or subsystem clock source ? clock source generation for lcd controller ? buzzer output frequency generator ? timing tests in high-speed mode
watch timer s3c9484 /c9488/f9488 13- 2 watch timer control register (wtcon) watch timer control register (wtcon) f9h, r/w, reset: 00h lsb msb .7 .6 .5 .4 .3 .2 .1 .0 watch timer interrupt pending bit : 0 = interrupt is not pending (when write, pending bit cleared) 1 = interrupt is pending watch timer control selection bit : 0 = main system clock (fxx /128) 1 = sub system clock buzzer signal selection bits: 00 = 0.5 khz buzzer (buz) signal output 01 = 1 khz buzzer (buz) signal output 10 = 2 khz buzzer (buz) signal output 11 = 4 khz buzzer (buz) signal output watch timer enable bit: 0 = disable watch timer 1 = enable watch timer note: fxx is assumed to be 4.195 mhz watch timer interrupt enable bit : 0 = disable watch timer interrupt 1 = enable watch timer interrupt watch timer speed selection bits: 00 = set watch timer interrupt to 1.0s 01 = set watch timer interrupt to 0.5s 10 = set watch timer interrupt to 0.25s 11 = set watch timer interrupt to 3.91ms figure 13-1. watch timer control register (wtcon)
s3c9484/c9488/f9488 watch timer 13- 3 watch timer circuit diagram enable/disable wtcon.0 wtint wtcon.6 buzzer output f w /2 15 f w /2 14 f w /2 13 f w /2 7 f xx = selected clock between fx and fxt (4.195 mhz) f xt = subsystem clock (32,768 hz) f w = watch timer wtcon.7 f w 32.768 khz f xt fxx / 128 f lcd (2 khz) wtcon.5 wtcon.4 wtcon.3 wtcon.2 wtcon.1 mux selector circuit frequency dividing circuit clock selector f w / 64 (0.5 khz) fw/32 (1 khz) fw/16 (2 khz) fw/8 (4 khz) figure 13-1. watch timer circuit diagram
watch timer s3c9484 /c9488/f9488 13- 4 + programming tip ? using the watch timer display (3.91ms,4khz buzzer out) .include "c:\skstudio\include\reg\s3c9488.reg" vector 00h,f9488_int .org 003ch db 0ffh db 0ffh db 01100000b ;disable lvr db 00000011b ;sub oscillator,bt overflow, reset pin enalbe .org 100h reset: di ld wdtcon,#10101010b ld btcon,#0001011b ld clkcon,#00011000b ld sp,#0c0h ld sy m,#00h ld osccon,#00000000b ld p1conl,#10100110b ;buzzer output ld wtcon,#11111110b ;sub system clock, 4khz,3.91ms interval ei ;================================================================================ main jp main ;================================================================================ f9488_int tm wtcon,#01h ;check what interrupt pending bit is set jp nz,watch_t_int ;.......... iret watch_t_int and wtcon,#0feh xor p1,#01h ;port toggle whenever interrupt service ; routine is executed nop nop iret .end
s3c9484/c9488/f9488 lcd controller/dri ver 14- 1 14 lcd controller / driver overview the s3c9484/c9488/f9488 micro-controller can directly drive an up-to-19-digit (19-segment) lcd panel. the lcd module has the following components: ? lcd controller/driver ? display ram (00h-1 2h) for storing display data in page 1 ? 19 segment output pins (seg0 ? seg18) ? 8 common output pins (com0 - com7) bit settings in the lcd control register, lcdcon, determine the lcd frame frequency, duty and bias, and the segment pins used for display output. when a subsystem clock is selected as the lcd clock source, the lcd display is enabled even during stop and idle modes. the lcd voltage control register lcdvol switches contrast output to segment/port. lcd data stored in the display ram locations are transferred to the segment signal pins automatically without program control. lcd controller/ driver 8 8-bit data bus 8 19 com0-com7 seg0-seg18 figure 14-1. lcd function diagram
lcd controller/driver s3c9484/c9488/f94 88 14- 2 lcd circuit diagram com0 com7 f lcd segn seg4 seg3 seg2 seg1 seg0 note: f lcd = f w /2 4 , f w / 2 5 , f w /2 6 , f w /2 7 8 mux 18 12h.7 12h.6 12h.5 12h.4 12h.3 12h.2 12h.1 12h.0 nh.7 nh.6 nh.5 nh.4 nh.3 nh.2 nh.1 nh.0 00h.7 00h.6 00h.5 00h.4 00h.3 00h.2 00h.1 00h.0 segment driver mux n mux 0 seg18 seg17 seg16 seg15 seg14 lcd voltage control com control timing controller lcdcon lcdvol 8 8 8 8 figure 14-2. lcd circuit diagram
s3c9484/c9488/f9488 lcd controller/dri ver 14- 3 lcd ram address area ram addresses 00h-12h of page 1 are used as lcd data memory. when the bit value of a display segment is "1", the lcd display is turned on; when the bit value is "0", the display is turned off. display ram data are sent out through segment pins seg0-seg18 using a direct memory access (dma) method that is synchronized with the f lcd signal. if these ram addresses not used for lcd display, you can be allocated to general-purpose use. seg0 bit7 bit7 bit6 bit6 bit1 bit1 bit0 bit0 00h 01h seg1 seg17 bit7 bit7 bit6 bit6 bit1 bit1 bit0 bit0 11h 12h seg18 com0 com1 com6 com7 figure 14-3. lcd display data ram organization note in mds(such as sk-1000), before changing page(page0 page1), you must disable global interrupt(di) and during accessing page1, you don?t have to use ?call? instruction.
lcd controller/driver s3c9484/c9488/f94 88 14- 4 lcd control register (lcdcon), d0h the lcd control register lcdcon is mapped to ram addresses d0h. lcdcon controls these lcd functions: ? lcd module enable/disable control (lcdcon.7) ? lcd duty and bias selection (lcdcon.5- lcdcon.4) ? lcd dot on/off control bit (lcdcon.3- lcdcon.2) ? lcd clock frequency selection (lcdcon.1- lcdcon.0) the lcd clock signal determines the frequency of com signal scanning of each segment output. this is also referred to as the 'frame frequency? since lcd clock is generated by dividing the watch timer clock (fw), the watch timer must be enabled when the lcd display is turned on. reset clears the lcdcon register values to logic zero. this produces the following lcd control settings: ? lcd clock frequency is the watch timer clock (fw)/2 7 = 256 hz the lcd display can continue to operate during idle and stop modes if a subsystem clock is used as the watch timer source. lcd converter control register (lcdcon) d0h, r/w, reset: 00h lsb msb .7 .6 .5 .4 .3 .2 .1 .0 lcd module enable/disable bit: 0 = lcd module disable 1 = lcd module enable lcd duty and bias selection bits: 00 = 1/8 duty, 1/4 bias 01 = 1/4 duty, 1/3 bias 1x = static lcd mode selection bits: 00 = dot off signal 01 = dot on signal 1x = normal display lcd clock selection bits: 00 = (fw) / 2 7 01 = (fw) / 2 6 10 = (fw) / 2 5 11 = (fw) / 2 4 not used figure 14-4. lcd control register (lcdcon)
s3c9484/c9488/f9488 lcd controller/dri ver 14- 5 lcd voltage control register (lcdvol) the lcd voltage control register lcdvol is mapped to ram addresses d1h. lcdvol is used to control the lcd contrast up to 16 step contrast level. ? lcd contrast control enable/disable bit (lcdvol.7) ? lcd contrast segment output selection bits (lcdvol.0 -lcdvol.3) lcd voltage control register (lcdvol) d1h, r/w, reset: 0fh lsb msb .7 .6 .5 .4 .3 .2 .1 .0 segment/port output selection bits: 0000 = 1/16 step (the dimmest level) 0001 = 2/16 step 0010 = 3/16 step 0011 = 4/16 step - - - - - 1110 = 15/16 step 1111 = 16/16 step lcd contrast control enable/disable bit: 0 = disable lcd contrast control 1 = enable lcd contrast control not used figure 14-5. lcd drive voltage control register (lcdvol)
lcd controller/driver s3c9484/c9488/f94 88 14- 6 note: when lcdvol.7 is logic one, you can control lcd contrast by writing data to lcdvol.3-.0 figure 14-6. internal voltage dividing resistor connection (1/4 bias, display on)
s3c9484/c9488/f9488 lcd controller/dri ver 14- 7 note: when lcdvol.7 is logic one, you can control lcd contrast by writing data to lcdvol.3-.0 figure 14-7. internal voltage dividing resistor connection (1/3 bias, display on)
lcd controller/driver s3c9484/c9488/f94 88 14- 8 lcd drive voltage the lcd display is turned on only when the voltage difference between the common and segment signals is greater than v lcd . the lcd display is turned off when the difference between the common and segment signal voltages is less than v lcd. the turn-on voltage, + v lcd or - v lcd , is generated only when both signals are the selected signals of the bias. table 14-1 shows lcd drive voltages level for static mode, 1/3 bias, 1/4 bias. table 14-1. lcd drive bias voltages level values lcd power supply static mode 1/3 bias 1/4 bias v lc4 v lcd ? v lcd v lc3 ? v lcd 3/4 v lcd v lc2 ? 2/3 v lcd 2/4 v lcd v lc1 ? 1/3 v lcd 1/4 v lcd v ss 0 v 0 v 0 v note: the lcd panel display may be deteriorated if a dc voltage is applied that lies between the common and segment signal voltage. therefore, always drive the lcd panel with ac voltage.
s3c9484/c9488/f9488 lcd controller/dri ver 14- 9 lcd seg/com signals the 19 lcd segment signal pins are connected to corresponding display ram locations at 00h-12h. bits 0-7 of the display ram are synchronized with the common signal output pins com0, . . . . , and com7. when the bit value of a display ram location is "1", a select signal is sent to the corresponding segment pin. when the display bit is "0", a 'no-select' signal is sent to the corresponding segment pin. each bias has select and no- select signals. lcd clock select non-select com v lc4 v ss seg com-seg v lc4 v ss v lc4 v ss -v lc4 1 frame figure 14-8. select/no-select bias signals in static display mode lcd clock select non-select 1 frame v lc3 v ss v lc2 v lc1 v lc3 v ss v lc2 v lc1 com seg com-seg v lc3 v ss v lc2 v lc1 -v lc1 -v lc2 -v lc3 figure 14-9. select/no-select bias signals in 1/4 duty, 1/3 bias display mode
lcd controller/driver s3c9484/c9488/f94 88 14- 10 lcd clock select non-select 1 frame v lc3 v ss v lc2 v lc1 v lc3 v ss v lc2 v lc1 com seg com-seg v lc3 v ss v lc2 v lc1 -v lc1 -v lc2 -v lc3 v lc4 v lc4 v lc4 -v lc4 figure 14-10. select/no-select bias signals in 1/8 duty, 1/4 bias display mode
s3c9484/c9488/f9488 lcd controller/dri ver 14- 11 v lc4 v ss v lc1 com0 com1 com3 seg0 com0 -seg0 com0 -seg1 com1 -seg1 com2 fr seg1 com1 -seg0 seg0.7 x c7 seg0.1 x c1 seg0.4 x c4 com0 com7 data register page 1, address 00h ld 00h, #5dh seg0 0 1 3 2 4 5 7 6 1 frame 0 1 3 2 4 5 7 6 v lc3 v lc2 v lc4 v ss v lc1 v lc3 v lc2 v lc4 v ss v lc1 v lc3 v lc2 -v lc1 -v lc2 -v lc3 -v lc4 com7 seg0.2 x c2 seg0.6 x c6 seg0.3 x c3 seg0.5 x c5 seg0.0 x c0 .0 .1 .2 .3 .4 .5 .6 .7 com1 com3 com2 com4 com6 com5 seg1 .0 .1 .2 .3 .4 .5 .6 .7 data register page1, address 01h ld 01h, #2eh 1 0 1 1 0 1 0 1 0 1 1 0 1 0 0 1 v lc4 v ss v lc1 v lc3 v lc2 v lc4 v ss v lc1 v lc3 v lc2 v lc4 v ss v lc1 v lc3 v lc2 v lc4 v ss v lc1 v lc3 v lc2 -v lc1 -v lc2 -v lc3 -v lc4 v lc4 v ss v lc1 v lc3 v lc2 -v lc1 -v lc2 -v lc3 -v lc4 v lc4 v ss v lc1 v lc3 v lc2 -v lc1 -v lc2 -v lc3 -v lc4 figure 14-11. lcd signal and wave forms example in 1/8 duty, 1/4 bias display mode
lcd controller/driver s3c9484/c9488/f94 88 14- 12 1 frame v ss v lc1 com0 com1 com3 seg0 com0 -seg0 com0 -seg1 com1 -seg1 com2 fr seg1 com1 -seg0 seg1.3 x c3 seg0.0 x c0 seg0.2 x c2 com0 data register page 1, address 00h ld 00h, #0eh seg0 0 1 3 2 v lc3 v lc2 v ss v lc1 v lc3 v lc2 -v lc1 -v lc2 -v lc3 seg1.1 x c1 seg0.3 x c3 seg0.1 x c1 seg1.2 x c2 seg1.0 x c0 .0 .1 .2 .3 .4 .5 .6 .7 com1 com3 com2 seg2 .0 .1 .2 .3 .4 .5 .6 .7 data register page 1, address 02h ld 02h, #03h 0 1 3 2 v ss v lc1 v lc3 v lc2 v ss v lc1 v lc3 v lc2 v ss v lc1 v lc3 v lc2 v ss v lc1 v lc3 v lc2 v ss v lc1 v lc3 v lc2 -v lc1 -v lc2 -v lc3 v ss v lc1 v lc3 v lc2 -v lc1 -v lc2 -v lc3 v ss v lc1 v lc3 v lc2 -v lc1 -v lc2 -v lc3 .0 .1 .2 .3 .4 .5 .6 .7 0 1 1 x x x x 1 1 1 0 x x x x 0 1 1 0 x x x x 0 0 1 1 x x x x 0 seg1 .0 .1 .2 .3 .4 .5 .6 .7 seg3 data register page 1, address 01h ld 01h, #03h data register page12, address 03h ld 03h, #06h figure 14-12. lcd signals and wave forms example in 1/4 duty, 1/3 bias display mode
s3c9484/c9488/f9488 lcd controller/dri ver 14- 13 + programming tip ? using the lcd display .include "c:\skstudio\include\reg\s3c9488.reg" lcd_data0_p1 .equ 00h .org 003ch db 0ffh db 0ffh db 01100000b db 00000011b ;smart option setting .org 100h reset: di ld wdtcon,#10101010b ld btcon,#0001011b ld clkcon,#00011000b ld sp,#0c0h ld sym,#00h ld osccon,#00000000b ld lcdcon,#10001000b ;1/8 duty,1/4 bias,fw/128 ld lcdvol,#10001111b ;lcd contrast enable,16/16 step ld p0conh,#0ffh ;com4-com7 ld p0conl,#11101010b ld p1conh,#0ffh ;com0-com3 ld p1pur,#00h ld p2conh,#0ffh ;seg7-seg10 ld p2conl,#0ffh ;seg3-seg6 ld p3conh,#10101011b ;seg18 ld p3conl,#11111111b ;seg15-se g17 ld p4conh,#00111111b ;seg12-seg14 ld p4conl,#0ffh ;seg0-seg2,seg11 ld wtcon,#02h ;watch timer enable ;================================================================================
lcd controller/driver s3c9484/c9488/f94 88 14- 14 main ld sym,#01h ;select page1 ld r0,#lcd_data0_p1 ;load lcd display data ram0 ld r2,#0 ld r3,#0 loop ldc r1,#lcd_data[rr2] ld @r0,r1 inc r0 inc r3 cp r3,#13h jp c,loop ld sym,#00h ;select page0 jp $ lcd_data .db 00h,48h,34h,0d0h,22h,11h,89h,0e2h,35h,0ffh .db 77h,33h,67h,99h,46h,0f1h,4h,8 8h,54h ;================================================================================ .end
s3c9484/c9488/f9488 a/d converter 15- 1 15 10-bit analog-to-digital converter overview the 10-bit a/d converter (adc) module uses successive approximation logic to convert analog levels entering at one of the nine input channels to equivalent 10 -bit digital values. the an alog input level must lie between the av ref and v ss values. the a/d converter has the following components: ? analog comparator with successive approximation logic ? d/a converter logic (resistor string type) ? adc control register (adcon) ? nine multiplexed analog data input pins (ad0 ? ad8) , alternately digital data i/o port ? 10-bit a/d conversion data output register (addatah/l) ? av ref pins, av ss is internally connected to v ss function description to initiate an analog-to-digital conversion procedure, at the first you must set port control register(p0conh/ p0conl/p1conl) for ad analog input. and you write the channel selection data in the a/d converter control register adcon.4-.6 to select one of the eight analog input pins (ad0-8) and set the conversion start bit, adcon.0. the read-write adcon register is located at address fch. the unused pin can be used for normal i/o. during a normal conversion, adc logic initially set the successive approximation register to 200h (the approximate half-way point of an 10 -bit register). this register is then updated automatically during each conversion step. the successive approximation block performs 10-bit conversions for one input channel at a time. you can dynamically select different channels by manipulating the channel selection bit value (adcon.7 - 4) in the adcon register. to start the a/d conversion, you should set the enable bit, adcon.0. when a conversion is completed, the end-of- conversion (eoc) bit is automatically set to 1 and the result is dumped into the addatah/l register where it can be read. the a/d converter then enters an idle state. remember to read the contents of addatah/l before another conversion starts. otherwise, the previous result will be overwritten by the next conversion result. note because the a/d converter does not use sample-and-hold circuitry, it is very important that fluctuation in the analog level at the ad0-ad8 input pins during a conversion procedure be kept to an absolute minimum. any change in the input level, perhaps due to noise, will invalidate the result. if the chip enters to stop or idle mode in conversion process, there will be a leakage current path in a/d block . you must use stop or idle mode after adc operation is finished.
a/d converter s3c9 484/c9488/f9488 15- 2 conversion timing the a/d conversion process requires 4 steps (4 clock edges) to convert each bit and 10 clocks to set-up a/d conversion. therefore, total of 50 clocks are required to complete an 10-bit conversion: when fxx/8 is selected for conversion clock with an 8 mhz fxx clock frequency, one clock cycle is 1 us. each bit conversion requires 4 clocks, the conversion rate is calculated as follows: 4 clocks/bit 10 bits + set-up time = 50 clocks, 50 clock 1us = 50 us at 1 mhz a/d converter control register (adcon) the a/d converter control register, adcon, is located at address fch. it has three functions: ? analog input pin selection (bits 4, 5, 6, and 7) ? a/d conversion end-of-conversion (eoc) status (bit 3) ? a/d conversion speed sel ection (bits 1,2) ? a/d operation start (bit 0) after a reset, the start bit is turned off. you can select only one analog input channel at a time. other analog input pins (adc0?adc8) can be selected dynamically by manipulating the adcon.4?6 bits. and the pins not used for analog input can be used for normal i/o function. a/d converter control register (adcon) fch, r/w lsb msb .7 .6 .5 .4 .3 .2 .1 .0 a/d input pin selection bits: 0000 = adc0 0001 = adc1 0010 = adc2 0011 = adc3 0100 = adc4 0101 = adc5 0110 = adc6 0111 = adc7 1000 = adc8 other values = connected with gnd internally a/d conversion start bit: 0 = disable operation 1 = start operation (auto-clear) clock source selection bits: 00 = fxx/16 (fosc = 8mhz) 01 = fxx/ 8 (fosc = 8mhz) 10 = fxx/ 4 (fosc = 8mhz) 11 = fxx (fosc = 4mhz) end-of-conversion(eco) status bit: 0 = a/d conversion is in progress 1 = a/d conversion complete maximum adc clock input = 4mhz figure 15-1. a/d converter control register (adcon)
s3c9484/c9488/f9488 a/d converter 15- 3 conversion data register high byte (addatah) fah, ready only lsb msb .7 .6 .5 .4 .3 .2 .1 .0 conversion data register low byte (addatal) fbh, ready only lsb msb x x x x x x .1 .0 figure 15-2. a/d converter data register (addatah/l) internal reference voltage levels in the adc function block, the analog input voltage level is compared to the reference voltage. the analog input level must remain within the range v ss to av ref (usually, av ref = v dd ). different reference voltage levels are generated internally along the resistor tree during the analog conversion process for each conversion step. the reference voltage level for the first conversion bit is always 1/2 av ref .
a/d converter s3c9 484/c9488/f9488 15- 4 block diagram - a/d converter control register adcon (fch) adcon.7-.4 m u l t i p l e x e r control circuit + - d/a converter v dd v ss successive approximation circuit analog comparator clock selector adcon.0 (adc start) adcon.2-.1 conversion result addatah (fah) addatal (fbh) to data bus adcon.3 (eoc flag) adc0/p1.3 adc1/p1.2 adc2/p1.1 adc7/p0.4 adc8/p0.3 figure 15-3. a/d converter functional block diagram
s3c9484/c9488/f9488 a/d converter 15- 5 internal a/d conversion procedure 1. analog input must remain between the voltage range of v ss and av ref . 2. configure p0.3?p0.7 and p1.0?p1.3 for analog input before a/d conversions. to do this, you have to load the appropriate value to the p0conh, p0conl and p1conl (for adc0?adc8) registers. 3. before the conversion operation starts, you must first select one of the eight input pins (adc0?adc8) by writing the appropriate value to the adcon register. 4. when conversion has been completed, (50 clocks have elapsed), the eoc, adcon.3 flag is set to "1", so that a check can be made to verify that the conversion was successful. 5. the converted digital value is loaded to the output register, addatah (8-bit) and addatal (2-bit), then the adc module enters an idle state. 6. the digital conversion result can now be read from the addatah and addatal register. v dd 103 reference voltage input s3c9484/c9488/ f9488 av ss av ref adc0-adc8 v dd c 101 c analog input pin 10pf note: the symbol 'r' signifies an offset resistor with a value of from 50 to 100. if this resistor is omitted, the absolute accuracy will be maximum of 3 lsbs. figure 15-4 recommended a/d converter circuit for highest absolute accuracy
a/d converter s3c9 484/c9488/f9488 15- 6 notes
s3c9484/c9488/f9488 watchd og timer 16- 1 16 watchdog timer overview whatchdog timer you can use the watchdog timer : ? watchdog timer provides an automatic reset mechanism with counter clock source of internal rc ring oscillation or basic timer overflow signal. ? watchdog timer can run in unin tentional stop/idle mode with internal rc ring oscillator. this prevents mcu from remaining in the abnormal stop/idle mode. the functional components of the watchdog timer block are: ? internal rc oscillation or basic timer overflow signal. ? smart option 3fh.1 selects counter clock source, 16bit watchdog timer overflow condition (bit15 ovf with internal ring oscillator or bit3 ovf with basic timer overflow). also, on stop and idle mode with internal rc ring oscillator, watchdog timer counter is not cleared by smart option. ? watchdog timer control register, wdtcon (e5h, read/write) ? 16bit watchdog timer counter watchdog timer control register (wdtcon) watchdog timer control register (wdtcon) e5h, r/w, reset: 00h lsb msb .7 .6 .5 .4 .3 .2 .1 .0 watchdog timer enable bits: 1010b = disable watchdog function other value = enable watchdog function watchdog timer counter clear bits: 1010b = clear watchdog timer counter other value = don't care figure 16-1. watchdog timer control register (wdtcon)
watchdog timer s3c9 484/c9488/f9488 16- 2 watchdog timer function description watchdog timer function you can program the watchdog timer overflow signal (wdtovf) to generate a reset by setting wdtcon.7-.4 to any value other than "1010b". (the "1010b" value disables the watchdog function.) a reset clears wdtcon to "00h", automatically enabling the watchdog timer function. the mcu is reset whenever a watchdog timer counter overflow occurs, during normal operation, the application program must prevent from the overflow, to do this, the wdtcnt value must be cleared (by writing a ?1010 ? to wdtcon.0-.3) at regular intervals. if a malfunction occurs due to noise or some other error conditions, the watchdog counter clear operation will not be executed by chip malfunction. so, before long, a watchdog timer overflow reset will occur. after this reset, chip will carry out normal operation again. in other words, during the normal operation, the watchdog timer overflow (bit 3 overflow or bit 15 overflow of the 16-bit watchdog timer counter, wdtcnt) does not occur by a 16bit watchdog timer counter clear operation. watchdog timer counter clock sources selection you can select counter clock source between basic timer overflow signal and internal rc ring oscillator. if you use basic timer overflow clock source, wdt overflow will occur at the time when counter bit 3 is set. if you use internal rc ring oscillator clock source, wdt overflow will occur at the time when counter bit 15 is set. watchdog timer in stop/idle mode 1. if the basic timer overflow signal is selected for the wdt counter clock source, wdt will be disabled automatically by hardware. so system reset can not occur by wdt. wdt counter is cleared automatically in stop/idle mode. in this case, current consumption is very small. 2. if internal rc ring oscillator is selecte d for the wdt counter clock source, wdt can be enabled in unintentional stop/idle mode. so system reset can occur by wdt. wdt counter is not cleared in stop/idle mode. so, when abnormal stop or idle mode occurs by noise, mcu can be returned to normal operation by wdt overflow reset. but, at this case, stop/idle mode current consumption becomes larger. if noise problem (like chip entering to unintentional stop/idle mode) is more important, you had better use internal rc ring oscillator. before running system, you must select smart option (3fh.1) for wdt counter source. if you select internal rc oscillator, normally, you must set watchdog timer to be disable before entering to stop mode. because, if wdt is not disabled, reset operation will occur by wdt counter overflow. if you want to use wdt in stop/idle mode for noise problem, current may drain too much by internal rc oscillation. so, if noise issue is not important, you had better select basic timer overflow signal for wdt counter clock source. watchdog timer counter overflow time for reset 1. if the basic timer overflow signal is selected for the wdt counter clock source and main clock, fxx, is 8mhz, basic timer clock fxx/128 fxx/1024 fxx/4096 time for wdt overflow 32.76msec 262msec 1.05sec 2. if internal rc ring oscillator is selected for the wdt counter clock source, timer for wdt overflow = (1/3.47) m sec x 2 16 = 18.89msec
s3c9484/c9488/f9488 watchd og timer 16- 3 rc 3.47mhz ring osc bit 3 ovf reset reset wdtcon .7-.4 16bit watchdog timer up-counter m u x smart option 3fh.1 m u x basic timer ovf wdtcon .7-.4 bit 15 ovf wdtcon .3 -.0 mux mux smart option 3fh.1 idle stop figure 16-2. watchdog timer block diagram
watchdog timer s3c9 484/c9488/f9488 16- 4 notes
s3c9484/c9488/f9488 voltage level dete ctor 17- 1 17 voltage level detector overview the s3c9484/c9488/f9488 micro-controller has a built-in vld(voltage level detector) circuit which allows detection of power voltage drop through software. turning the vld operation on and off can be controlled by software. because the ic consumes a large amount of current during vld operation. it is recommended that the vld operation should be kept off unless it is necessary. also the vld criteria voltage can be set by the software. the criteria voltage can be set by matching to one of the 3 kinds of voltage 2.4v, 2.7v, 3.3v or 3.9v (vdd reference voltage). the vld block works only when vldcon.0 is set. if vdd level is lower than the reference voltage selected with vldcon.5-.1, vldcon.6 will be set. if vdd level is higher, vldcon.6 will be cleared. please do not operate the vld block for minimize power current consumption. reference voltage selection bit 10110 = 2.4 v 10011 = 2.7 v 01110 = 3.3 v 01011 = 3.9 v vld operation enable bit 0 = operation off 1 = operation on voltage level set bit (read only) 0 = v dd is higher than reference voltage 1 = v dd is lower than reference voltage voltage level detector control register (vldcon) d8h, r/w,bit6 read-only, reset value:2ch lsb msb .7 .6 .5 .4 .3 .2 .1 .0 not used figure 17-1. vld control register (vldcon)
voltage level detector s3c9484/c9488/f9 488 17- 2 voltage level detector vld out v dd pin voltage level setting vldcon.6 vldcon.0 vldcon.5~ vldcon.1 vld run set the level figure 17-2. block diagram for voltage level detect
s3c9484/c9488/f9488 voltage level dete ctor 17- 3 voltage level detector control register (vldcon) the bit 0 of vldcon controls to run or disable the operation of voltage level detector. basically this v vld is set as 2.4 v by system reset and it can be changed in 4 kinds voltages by selecting voltage level detector control register(vldcon). when you write 5 bit data value to vldcon, an established resistor string is selected and the v vld is fixed in accordance with this resistor. table 17-1 shows specific v vld of 3 levels. + - v ref bgr v ref v in v dd comparator v dd voltage level detector control register (vldcon) d8h, r/w,bit6 read-only, reset value:2ch lsb .7 .6 .5 .4 .3 .2 .1 .0 figure 17-2. voltage level detect circuit and control register table 17-1. vldcon value and detection level vldcon .5-.1 v vld 10110 2.4 v 10011 2.7 v 01110 3.3 v 01011 3.9 v note: vldcon reset value is 2ch .
voltage level detector s3c9484/c9488/f9 488 17- 4 voltage(vdd) level detection sequence - vld usage step 0: don?t make vld on in normal conditions for small current consumption. step 1: for initializing analog comparator, write #3fh to vldcon. (comparator initialization, vld enable) step 2: write value to reference voltage setting bits in vldcon. (voltage setting, vld enable) step 3: wait 10~20usec for comparator operation time. (wait compare time) step 4: check result by loading voltage level set bit in vldcon. (check result) step 5: for another measurement, repeat above steps . programing tip ld vldcon,#3fh ; comparator initialization,vld enable (step 1) ld vldcon,#00011101b ; 3.3v detection voltage setting, vld enable (step 2) nop nop nop ? ; wait 10~20usec (step 3) ? ? ld r0, vldcon ; load vldcon to r0 (step 4) tm r0, #01000000b ; check bit6 of r0. if bit6 is ?h?, vdd is lower than 3.3v. jp nz, low_vdd ; if not zero(bit 6 is ?h?), jump to ?low_vdd? routine. table 17-2. characteristics of voltage level detect circuit (t a = 25 c) parameter symbol conditions min typ max unit operating voltage v ddvld 1.5 ? 5.5 v detection voltage v vld vldcon.5?.1 = 10110b 2.0 2.4 2.8 vldcon.5?.1 = 10011b 2.3 2.7 3.1 vldcon.5?.1 = 01110b 2.9 3.3 3.7 vldcon.5?.1 = 01011b 3.5 3.9 4.3 current consumption i vld vld on v dd = 5.5 v ? 65 100 ua v dd = 3.0 v 45 80
s3c9484/c9488/f9488 voltage level dete ctor 17- 5
s3c9484/c9488/f9488 low voltage reset 18- 1 18 low voltage reset overview the s3c9484/c9488/f9488 can be reset in four ways: ? by external power-on-reset ? by the external reset input pin pulled low ? by the digital watchdog timing out ? by the low voltage reset cir cuit (lvr) during an external power-on reset, the voltage vdd is high level and the resetb pin is forced low level. the resetb signal is input through a schmitt trigger circuit where it is then synchronized with the cpu clock. this brings the s3c9484/c9488/f9488 into a known operating status. to ensure correct start-up, the user should take that reset signal is not released before the vdd level is sufficient to allow mcu operation at the chosen frequency. the resetb pin must be held to low level for a minimum time interval after the power supply comes within tolerance in order to allow time for internal cpu clock oscillation to stabilize. the minimum required oscillation stabilization time for a reset is approximately 8.19 ms ( @ 2 16 /fosc, fosc= 8mhz). when a reset occurs during normal operation (with both vdd and resetb at high level), the signal at the resetb pin is forced low and the reset operation starts. all system and peripheral control registers are then set to their default hardware reset values (see table 8-1). the mcu provides a watchdog timer function in order to ensure graceful recovery from software malfunction. if watchdog timer is not refreshed before an end-of-counter condition (overflow) is reached, the internal reset will be activated. the s3c9484/c9488/f9488 has a built-in low voltage reset circuit that allows detection of power voltage drop of external v dd input level to prevent a mcu from malfunctioning in an unstable mcu power level. this voltage detector works for the reset operation of mcu. this low voltage reset includes an analog comparator and vref circuit. the value of a detection voltage is set internally by hardware. the on-chip low voltage reset, features static reset when supply voltage is below a reference voltage value (you did select at smart option 3fh). thanks to this feature, external reset circuit can be removed while keeping the application safety. as long as the supply voltage is below the reference value, there is an internal and static reset. the mcu can start only when the supply voltage rises over the reference voltage. when you calculate power consumption, please remember that a static current of lvr circuit should be added a cpu operating current in any operating modes such as stop, idle, and normal run mode.
low voltage reset s 3c9484/c9488/f9488 18 - 2 + - v ref bgr v dd v ref v in v dd n.f internal system resetb when the v dd level is lower than 2.7v comparator notes: 1. the target of voltage detection level is that you did select at smart option 3eh. 2. bgr is band gap voltage reference longger than 1us n.f reset watchdog reset longger than 1us smart option 3eh.7 smart option 3eh.7 smart option 3fh.0 figure 18-1. low voltage reset circuit note to program the duration of the oscillation stabilization interval, you make the appropriate settings to the basic timer control register, btcon, before entering stop mode. also, if you do not want to use the watchdog function (which causes a system reset if a watchdog timer counter overflow occurs), you can disable it by writing '1010b' to the upper nibble of wdtcon.
s3c9484/c9488/f9488 electrical data 19- 1 19 electrical data overview in this chapter, s3c9484/c9488/f9488 electrical characteristics are presented in tables and graphs. the information is arranged in the following order: ? absolute maximum ratings ? input/output capacitance ? d.c. electrical characteristics ? a.c. electrical characteristics ? oscillation characteristics ? oscillation stabilization time ? data retention supply voltage in stop mode ? a/d converter electrical characteristics
electrical data s3c 9484/c9488/f9488 19- 2 table 19-1. absolute maximum ratings (t a = 25 c) parameter symbol conditions rating unit supply voltage v dd ? 0.3 to +6.5 v input voltage v i ? 0.3 to v dd + 0.3 output voltage v o ? 0.3 to v dd + 0.3 output current high i oh one i/o pin active ? 18 ma all i/o pins active ? 60 output current low i ol one i/o pin active +30 total pin current for port +100 operating temperature t a ? 25 to + 85 c storage temperature t stg ? 65 to + 150 table 19-2. d.c. electrical characteristics (t a = -25 c to + 85 c, v dd = 2.2 v to 5.5 v) parameter symbol conditions min typ max unit operating voltage v dd f cpu = 8 mhz 2.7 ? 5.5 v f cpu = 4 mhz 2.2 5.5 input high voltage v ih1 all input pins except v ih2 0.8 v dd v dd v ih2 x in , xt in v dd -0.5 input low voltage v il1 all input pins except v il2 ? 0.2 v dd v il2 x in , xt in 0.5
s3c9484/c9488/f9488 electrical data 19- 3 table 19-2. d.c. electrical characteristics (continued) (t a = -25 c to + 85 c, v dd = 2.2 v to 5.5 v) parameter symbol conditions min typ max unit output high voltage v oh1 v dd = 2.4 v; i oh = -4 ma p1.0-p1.1 and p3.4-p3.6 v dd - 0.7 v dd - 0.3 ? v v oh2 v dd = 5 v; i oh = -4 ma port 2 v dd - 1.0 ? ? v oh3 v dd = 5 v; i oh = -1 ma normal output pins v dd - 1.0 ? ? output low voltage v ol1 v dd = 2.4 v; i ol = 12 ma p1.0-p1.1 and p3.4-p3.6 0.3 0.5 v ol2 v dd = 5 v; i ol = 15 ma port 2 0.4 2.0 v ol3 v dd = 5 v; i ol = 4 ma normal output pins ? 0.4 2.0 input high leakage current i lih1 v in = v dd all input pins except i lih2 ? ? 3 m a i lih2 v in = v dd, x in , xt in 20 input low leakage current i lil1 v in = 0 v all input pins except i lil2 ? ? -3 i lil2 v in = 0 v, x in , xt in -20 output high leakage current i loh v out = v dd all i/o pins and output pins ? ? 3 output low leakage current i lol v out = 0 v all i/o pins and output pins ? ? -3 oscillator feed back resistors r osc1 v dd = 5.0 v, t a = 25 c x in = v dd , x out = 0 v 800 1000 1200 k w pull-up resistor r l1 v in = 0 v; v dd = 5 v 10 % port 0,1,2,3,4 t a = 25 c 25 50 100 com output voltage deviation v dc v dd = v lc4 = 5 v (v lc4 -comi) io = 15 p- m a (i = 0-7) ? 45 90 mv seg output voltage deviation v ds v dd = v lc4 = 5 v (v lc4 -segi) io = 15 p- m a (i = 0-18) ? 45 90
electrical data s3c 9484/c9488/f9488 19- 4 table 19-2. d.c. electrical characteristics (concluded) (t a = -25 c to + 85 c, v dd = 2.2v to 5.5 v) parameter symbo l conditions min typ max unit lcd voltage dividing resister r lcd _ 40 75 100 k w v lc3 output voltage v lc3 v dd =1.8v to 5.5v, 1/4 bias lcd clock=0hz, v lc4 =v dd 0.75v dd -0.2 0.75v dd 0.75v dd+ 0.2 v v lc2 output voltage v lc2 0.5v dd -0.2 0.5v dd 0.5v dd +0.2 v v l c1 output voltage v lc1 0.25v dd -0.2 0.25v dd 0.25v dd+ 0.2 v supply current (1) i dd1 (2) v dd = 5 v 10 % 8 mhz crystal oscillator ? 12 25 ma 4 mhz crystal oscillator 4 10 v dd = 3 v 10 % 8 mhz crystal oscillator 3 8 4 mhz crystal oscillator 1 5 i dd2 idle mode: v dd = 5 v 10 % 8 mhz crystal oscillator 3 10 4 mhz crystal oscillator 1.5 4 idle mode: v dd = 3 v 10 % 8 mhz crystal oscillator 1.2 3 4 mhz crystal oscillator 1.0 2.0 i dd3 sub operating: main-osc stop v dd = 3 v 10 % 32768 hz crystal oscillator 40 80 m a i dd4 sub idle mode: main osc stop v dd = 3 v 10 % 32768 hz crystal oscillator 7 14 i dd5 main stop mode : sub-osc stop v dd = 5 v 10 %, t a = 25 c 1 3 v dd = 3 v 10 %, t a = 25 c 0.5 2 notes: 1. supply current does not include current drawn through internal pull-up resistors or external output current loads. 2. i dd1 and i dd2 include a power consumption of subsystem oscillator. 3. i dd3 and i dd4 are the current when the main system clock oscillation stop and the subsystem clock is used. and they does not include the lcd and voltage booster and voltage level detector current. 4. i dd5 is the current when the main and subsystem clock oscillation stop. 5. voltage booster?s operating voltage rage is 2.0v to 5.5v. 6. if you use lvr module, supply current increase. (refer to table 19-12)
s3c9484/c9488/f9488 electrical data 19- 5 table 19-3. a.c. electrical characteristics (t a = -25 c to +85 c, v dd = 2.2 v to 5.5 v) parameter symbol conditions min typ max unit interrupt input high, low width (p3.3?p3.6) t inth , t intl p3.3?p3.6, v dd = 5 v 200 ? ? ns reset input low width t rsl v dd = 5 v 1.5 ? ? m s note: user must keep more large value then min value. t intl 0.8 v dd 0.2 v dd t inth 0.2 v dd figure 19-1. input timing for external interrupts (p3.3?p3.6) reset t rsl 0.2 v dd figure 19-2. input timing for reset
electrical data s3c 9484/c9488/f9488 19- 6 table 19-4. input/output capacitance (t a = -25 c to +85 c, v dd = 0 v ) parameter symbol conditions min typ max unit input capacitance c in f = 1 mhz; unmeasured pins are returned to v ss ? ? 10 pf output capacitance c out i/o capacitance c io table 19-5. data retention supply voltage in stop mode (t a = -25 c to + 85 c) parameter symbol conditions min typ max unit data retention supply voltage v dddr 2 ? 5.5 v data retention supply current i dddr v dddr = 2 v ? ? 3 m a execution of stop instrction reset occurs ~ ~ v dddr ~ ~ stop mode oscillation stabilization time normal operating mode data retention mode t wait reset v dd note: t wait is the same as 4096 x 16 x 1/f osc 0.2 v dd figure 19-3. stop mode release timing initiated by reset
s3c9484/c9488/f9488 electrical data 19- 7 execution of stop instruction ~ ~ v dddr ~ ~ stop mode idle mode data retention mode t wait v dd interrupt normal operating mode oscillation stabilization time 0.2 v dd note: t wait is the same as 4096 x 16 x bt clock figure 19-4. stop mode(main) release timing initiated by interrupts execution of stop instruction ~ ~ v dddr ~ ~ stop mode idle mode data retention mode t wait v dd interrupt normal operating mode oscillation stabilization time 0.2 v dd note: t wait = 128 x 16 x (1/32768) = 62.5 ms figure 19-5. stop mode(sub) release timing initiated by interrupts
electrical data s3c 9484/c9488/f9488 19- 8 table 19-6. a/d converter electrical characteristics (t a = - 25 c to +85 c, v dd = 2.2 v to 5.5 v, v ss = 0 v) parameter symbol conditions min typ max unit resolution ? 10 ? bit total accuracy v dd = 5.12 v ? ? 3 lsb integral linearity error ile av ref = 5.12v ? ? 3 differential linearity error dle av ss = 0 v cpu clock = 8 mhz ? ? 1 offset error of top eot ? 1 3 offset error of bottom eob ? 1 3 conversion time (1) t con 10-bit resolution 50 x fxx/4, fxx = 8mhz 20 ? ? m s analog input voltage v ian ? av ss ? av ref v analog input impedance r an ? 2 1000 ? m w analog reference voltage av ref ? 2.5 ? v dd v analog ground av ss ? v ss ? v ss +0.3 analog input current i adin av ref = v dd = 5v ? ? 10 m a analog block current (2) i adc av ref = v dd = 5v ? 1 3 ma av ref = v dd = 3v 0.5 1.5 av ref = v dd = 5v when power down mode 100 500 na notes: 1. 'conversion time' is the time required from the moment a conversion operation starts until it ends. 2. i adc is an operating current during a/d conversion.
s3c9484/c9488/f9488 electrical data 19- 9 v dd 103 reference voltage input s3c9484/c9488/ f9488 av ss av ref adc0-adc8 v dd c 101 c analog input pin 10pf note: the symbol 'r' signifies an offset resistor with a value of from 50 to 100. if this resistor is omitted, the absolute accuracy will be maximum of 3 lsbs. figure 19-6. recommended a/d converter circuit for highest absolute accuracy
electrical data s3c 9484/c9488/f9488 19- 10 table 19-7. main oscillator frequency (f osc1 ) (t a = -25 c to +85 c, v dd = 2.2 v to 5.5 v) oscillator clock circuit test condition min typ max unit crystal x in c1 c2 x out (1) crystal oscillation frequency (2) crystal = 8mhz c1 = 20 pf, c2 = 20 pf 1 ? 8 mhz ceramic x in c1 c2 x out ceramic oscillation frequency 1 ? 8 external clock x in x out x in input frequency 1 ? 8 rc x in x out r r = 35 k w , v dd = 5 v 2 notes: 1. we recommend crystal of tdk korea as the most suitable oscillator of samsung microcontroller. if you want to know detailed information of crystal oscillator frequency with cap, please visit the we b site(www.tdkkorea.co.kr). 2. the value of crystal(10mhz) and cap(20pf) is based on tdk korea parts. table 19-8. main oscillator clock stabilization time (t st1 ) (t a = -25 c to +85 c, v dd = 2.2v to 5.5 v) oscillator test condition min typ max unit crystal v dd = 4.5 v to 5.5 v ? ? 10 ms v dd = 2.2 v to 4.5 v 30 ceramic stabilization occurs when v dd is equal to the minimum oscillator voltage range. ? ? 4 external clock x in input high and low level width (t xh , t xl ) 50 ? ? ns note: oscillation stabilization time (t st1 ) is the time required for the cpu clock to return to its normal oscillation frequency after a power-on occurs, or when stop mode is ended by a reset signal.
s3c9484/c9488/f9488 electrical data 19- 11 x in t xh t xl 1/f osc1 v dd - 0.5 v 0.4 v figure 19-7. clock timing measurement at x in table 19-9. sub oscillator frequency (f osc2 ) (t a = -25 c + 85 c, v dd = 2.2 v to 5.5 v) oscillator clock circuit test condition min typ max unit crystal c1 c2 xt in xt out c1 = 33 pf, c2 = 33 pf 32 32.768 35 khz table 19-10. sub oscillator(crystal) stabilization time (t st2 ) (t a = 25 c, v dd = 2.2 v to 5.5 v)) test condition min typ max unit v dd = 4.5 v to 5.5 v ? 250 500 ms v dd = 2.2 v to 4.5 v ? ? 10 s note: oscillation stabilization time (t st2 ) is the time required for the cpu return to its normal operation when stop mode is released by interrupts. table 19-11. lcd contrast controller characteristics ( t a = ? 25 c to + 85 c, v dd = 4.5 v to 5.5 v) parameter symbol conditions min typ max unit resolution ? ? ? ? 4 bits linearity rlin ? ? ? 1.0 lsb max output voltage (lcdvol=#8fh) vlpp vlc4=v dd =5v 4.9 ? vlc1 v
electrical data s3c 9484/c9488/f9488 19- 12
s3c9484/c9488/f9488 electrical data 19- 13 table 19-12. lvr (low voltage reset) circuit characteristics (t a = 25 c) parameter symbol test condition min typ max unit lvr voltage high v lvrh 2.8 3.5 4.1 v lvr voltage low v lvrl 2.4 3.1 3.7 2.6 3.3 3.9 2.8 3.5 4.1 power supply voltage rising time t r 10 m s power supply voltage off time t off 0.5 s lvr circuit consumption i ddpr v dd = 5v +/- 10% 65 100 m a current v dd = 3v 45 80 notes: 1. 2 16 /fx ( = 8.19ms at fx = 8 mhz) 2. current consumed when low voltage reset circuit is provided internally. v dd t r t off t ddh t ddl figure 19-8. lvr (low voltage reset) timing
electrical data s3c 9484/c9488/f9488 19- 14 10 mhz 4mhz 1 mhz 5 6 7 supply voltage (v) minimum instruction clock = 1/4 x oscillator frequency 5.5 8 mhz 2.7 a b 4 3 2 1 f cpu 2.2 figure 19-9. operating voltage range
s3c9484/c9488/f9488 electrical data 19- 15 notes
s3c9484/c9488/f9488 mechanical data 20- 1 20 mechanical data overview the s3c9484/c9488/f9488 microcontroller is currently available in 32-sdip, 32-sop, 42-sdip, 44-qfp package. note : dimensions are in millimeters. 27.88 max 27.48 0 .20 (1.37) 32-sdip-400 9.10 0 .20 #32 #1 0.45 0.10 1.00 0.10 3.80 0.20 5.08 max 1.778 0.51 min 3.30 0.30 #17 #16 0-15 0.25 + 0.10 - 0.05 10.16 figure 20-1. 32-sdip-400 package dimensions
mechanical data s3c 9484/c9488/f9488 20- 2 32-sop-450a 20.30 max 19.90 0 .20 #17 #16 0-8 0.25 + 0.10 - 0.05 11.43 8.34 0 .20 0.90 0.20 0.05 min 2.00 0 .10 2.20 max 0.10 max 1.27 note : dimensions are in millimeters. 12.00 0 .30 #32 #1 (0.43) 0.40 0.10 figure 20-2. 32-sop-450a package dimensions
s3c9484/c9488/f9488 mechanical data 20- 3 note : dimensions are in millimeters. 39.50 max 39.10 0 .20 0.50 0 .10 1.78 (1.77) 0.51 min 3.30 0.30 3.50 0 .20 5.08 max 42-sdip-600 0-15 1.00 0.10 0.25 + 0.10 - 0.05 15.24 14.00 0 .20 #42 #22 #21 #1 figure 20-3. 42-sdip-600 package dimensions
mechanical data s3c 9484/c9488/f9488 20- 4 44-qfp-1010b #44 note : dimensions are in millimeters. 10.00 0.20 13.20 0.30 10.00 0.20 13.20 0.30 #1 0.35 + 0.10 - 0.05 0.80 0.10 max 0.80 0.20 0.05 min 2.05 0.10 2.30 max 0.15 + 0.10 - 0.05 0-8 0.15 max (1.00) figure 20-4. 44-qfp-1010 package dimensions
s3c9484/c9488/f9488 mtp 21- 1 21 mtp overview the S3F9488 single-chip cmos microcontroller is the mtp (multi time programmable) version of the s3c9484/c9488 microcontroller. it has an on-chip half flash rom instead of masked rom. the half flash rom is accessed by serial data format. the half flash rom can be rewritten up to 100 times. the S3F9488 is fully compatible with the s3c9484/c9488, in function, in d.c. electrical characteristics, and in pin configuration. because of its simple programming requirements, the S3F9488 is ideal for use as an evaluation chip for the s3c9484/c9488.
mtp s3c9484/c9488/f9 488 21- 2 p 2 . 3 / s e g 6 p 2 . 2 / s e g 5 p 2 . 1 / s e g 4 p 2 . 0 / s e g 3 p 4 . 2 / s e g 2 p 4 . 1 / s e g 1 p 4 . 0 / s e g 0 p 1 . 7 / c o m 0 p 1 . 6 / c o m 1 p 1 . 5 / c o m 2 p 1 . 4 / c o m 3 seg7/p2.4 seg8/p2.5 seg9/p2.6 seg10/p2.7 seg11/p4.3 seg12/p4.4 seg13/p4.5 seg14/p4.6 seg15/p3.0 seg16/rxd/p3.1 seg17/txd/p3.2 S3F9488 (top view) (44-qfp) 34 35 36 37 38 39 40 41 42 43 44 3 3 3 2 3 1 3 0 2 9 2 8 2 7 2 6 2 5 2 4 2 3 p1.3/adc0/ p1.2/adc1 p1.1/adc2/buz p1.0/adc3/tbpwm p0.7/com4/adc4 p0.6/com5/adc5 p0.5/com6/adc6 av ref p0.4/com7/adc7 p0.3/adc8 p0.2/ resetb 22 21 20 19 18 17 16 15 14 13 12 s e g 1 8 / i n t 0 / p 3 . 3 t a o u t / i n t 1 / p 3 . 4 s d a t / t a c k / i n t 2 / p 3 . 5 s c l k / t a c a p / i n t 3 / p 3 . 6 v d d x o u t t e s t / v p p x t i n / p 0 . 0 x t o u t / p 0 . 1 1 2 3 4 5 6 7 8 9 1 0 1 1 v s s x i n figure 21-1. pin assignment diagram (44-pin package)
s3c9484/c9488/f9488 mtp 21- 3 seg12/p4.4 seg13/p4.5 seg14/p4.6 seg15/p3.0 seg16/rxd/p3.1 seg17/txd/p3.2 seg18/int0/p3.3 taout/int1/p3.4 sdat /tack/int2/p3.5 sclk /tacap/int3/p3.6 v dd v ss x out x in vpp /test xt in /p0.0 xt out /p0.1 resetb /p0.2 av ref com6/adc6/p0.5 com5/adc5/p0.6 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 p4.3/seg11 p2.7/seg10 p2.6/seg9 p2.5/seg8 p2.4/seg7 p2.3/seg6 p2.2/seg5 p2.1/seg4 p2.0/seg3 p4.2/seg2 p4.1/seg1 p4.0/seg0 p1.7/com0 p1.6/com1 p1.5/com2 p1.4/com3 p1.3/adc0 p1.2/adc1 p1.1/adc2/buz p1.0/adc3/tbpwm p0.7/adc4/com4 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 24 23 22 S3F9488 (top view) 42-sdip figure 21-2. pin assignment diagram (42-pin package) v ss x i n x out vpp /test xt in /p0.0 xt out /p0.1 resetb /p0.2 av ref adc3/tbpwm/p1.0 buz/adc2/p1.1 adc1/p1.2 adc0/p1.3 com3/p1.4 com2/p1.5 com1/p1.6 com0/p1.7 S3F9488 (top view) 32-sop 32-sdip 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 v dd p3.6/int3/tacap/ sclk p3.5/int2/tack/ sdat p3.4/int1/taout p3.3/int0/seg18 p3.2/txd/seg17 p3.1/rxd/seg16 p3.0/seg15 p2.7/seg10 p2.6/seg9 p2.5/seg8 p2.4/seg7 p2.3/seg6 p2.2/seg5 p2.1/seg4 p2.0/seg3 32 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 figure 21-3. pin assignment diagram (32-pin package)
mtp s3c9484/c9488/f9 488 21- 4 table 21-1. descriptions of pins used to read/write the flash rom main chip during programming pin name pin name pin no. i/o function p3.5 sdat 3 (44-pin) 9 (42-pin) 30 (32-pin) i/o serial data pin (output when reading, input when writing) input and push-pull output port can be assigned p3.6 sclk 4 (44-pin) 10 (42-pin) 31 (32-pin) i serial clock pin (input only pin) test vpp 9 (44-pin) 15 (42-pin) 4 (32-pin) i power supply pin for flash rom cell writing (indicates that mtp enters into the writing mode). when 12.5 v is applied, mtp is in writing mode and when 5 v is applied, mtp is in reading mode. (option) p0.2 resetb 12 (44-pin) 18 (42-pin) 7 (32-pin) i v dd /v ss v dd /v ss 5/6 (44-pin) 11/12 (42-pin) 32/1 (32-pin) i logic power supply pin. table 21-2. comparison of S3F9488 and s3c9484/c9488 features characteristic S3F9488 s3c9484/c9488 program memory 8 kbyte flash rom 4k/8k byte mask rom operating voltage (v dd ) 2.2(2.7) v to 5.5 v 2.2(2.7) v to 5.5 v mtp programming mode v dd = 5 v, v pp = 12.5 v pin configuration 44qfp / 42sdip / 32sdip/ 32sop eprom programmability user program multi time programmed at the factory
s3c9484/c9488/f9488 development tools 22- 1 22 development tools overview samsung provides a powerful and easy-to-use development support system on a turnkey basis. the development support system is composed of a host system, debugging tools, and supporting software. for a host system, any standard computer that employs win95/98/2000/xp as its operating system can be used. a sophisticated debugging tool is provided both in hardware and software: the powerful in-circuit emulator, smds2+ or sk-1000, for the s3c7-, s3c9-, and s3c8- microcontroller families. smds2+ is a newly improved version of smds2, and sk- 1000 is supported by a third party tool vendor. samsung also offers supporting software that includes, debugger, an assembler, and a program for setting options. shine samsung host interface for in-circuit emulator, shine, is a multi-window based debugger for smds2+. shine provides pull-down and pop-up menus, mouse support, function/hot keys, and context-sensitive hyper-linked help. it has an advanced, multiple-windowed user interface that emphasizes ease of use. each window can be easily sized, moved, scrolled, highlighted, added, or removed. sasm the sasm takes a source file containing assembly language statements and translates them into a corresponding source code, an object code and comments. the sasm supports macros and conditional assembly. it runs on the ms-dos operating system. as it produces the re-locatable object codes only, the user should link object files. object files can be linked with other object files and loaded into memory. sasm requires a source file and an auxiliary register file (device_name.reg) with device specific information. sama assembler the samsung arrangeable microcontroller (sam) assembler, sama, is a universal assembler, and generating an object code in the standard hexadecimal format. assembled program codes include the object code used for rom data and required in-circuit emulators program control data. to assemble programs, sama requires a source file and an auxiliary definition (device_name.def) file with device specific information. hex2rom hex2rom file generates a rom code from a hex file which is produced by the assembler. a rom code is needed to fabricate a microcontroller which has a mask rom. when generating a rom code (.obj file) by hex2rom, the value "ff" is automatically filled into the unused rom area, up to the maximum rom size of the target device.
development tools s 3c9484/c9488/f9488 22- 2 target boards target boards are available for all the s3c9-series microcontrollers. all the required target system cables and adapters are included with the device-specific target board. tb9484/88 is a specific target board for the s3c9484/c9488/f9488 development bus emulator (smds2+ or sk-1000) rs-232c pod probe adapter eprom writer unit ram break/display unit trace/timer unit sam9 base unit power supply unit ibm-pc at or compatible tb9484/88 target board eva chip target application system figure 22-1. smds+ or sk-1000 product configuration
s3c9484/c9488/f9488 development tools 22- 3 tb9484/9488 target board the tb9484/9488 target board is used for the s3c9484/c9488/f9488 microcontrollers. it is supported by the sk-1000/smds2+ development systems. tb9484/88 smxxxx gnd v cc to user_v cc off on smds2 smds2+ j101 1 49 2 50 25 reset idle stop x-tal (32khz) 1 cn1 p0.0 p0.0 use port + + 50-pin connector 144-qfp s3e9480 eva chip 100-pin connector u2 74hc11 4dip sw rev.x 200x. xx. xx (rev0)rev1 (3eh.7)3fh.2 (3eh.0)3fh.1 (3eh.1)3fh.0 (3eh.2)3fh.7 figure 22-2. tb9484/88 target board configuration
development tools s 3c9484/c9488/f9488 22- 4 table 22-1. power selection settings for tb9484/88 "to user_vcc" settings operating mode comments to user_vcc off on target system sk-1000/smds2+ tb9484/88 v cc v ss v cc external the sk-1000/smds2+ main board supplies v cc to the target board (evaluation chip) and the target system. on to user_vcc off target system sk-1000/smds2+ tb9484/88 v cc v ss v cc external the sk-1000/smds2+ main board supplies v cc only to the target board (evaluation chip). the target system must have its own power supply. note : the following symbol in the "to user_vcc" setting column indicates the electrical short (off) configuration: smds2+ selection (sam8) in order to write data into program memory that is available in smds2+, the target board should be selected to be for smds2+ through a switch as follows. otherwise, the program memory writing function is not available. table 22-2. the smds2+ tool selection setting "sw1" setting operating mode smds smds2+ target system smds2+ r/w* r/w*
s3c9484/c9488/f9488 development tools 22- 5 on off 3fh.2 3fh.1 3fh.0 3eh.7 on low off high notes: 1. there is no rom in the evachip. so smart option is not determined by software but dip switch. 2. target board revision number is printed on the target board (refer to the figure 22-2.) : target board revision 1 3fh.7 3fh.0 3fh.1 3fh.2 : target board revision 0 figure 22-4. dip switch for smart option switch on off 3fh.2 xtin / xtout enable normal i/o pin enable 3fh.1 internal rc oscillator basic timer overflow used 3fh.0 normal i/o pin enable reset pin enable 3eh.7 lvr disable lvr enable
development tools s3 c9484/c9488/f9488 22- 6 seg18/int0/p3.3 tack/int2/p3.5 vdd n.c. test xtout/p0.1 adc8/p0.3 avref com5/adc5/p0.6 tbpwm/adc3/p1.0 adc1/p1.2 com3/p1.4 com1/p1.6 seg0/p4.0 seg2/p4.2 seg4/p2.1 seg6/p2.3 seg8/p2.5 seg10/p2.7 seg12/p4.4 seg14/p4.6 seg16/rxd/p3.1 n.c. n.c. n.c. s3c9228 (42-sdip) p3.4/int1/taout p3.6/int3/tacap vss n.c. p0.0/xtin p0.2/resetb p0.4/adc7/com7 p0.5/adc6/com6 p0.7/adc4/com4 p1.1/adc2/buz p1.3/adc0 p1.5/com2 p1.7/com0 p4.1/seg1 p2.0/seg3 p2.2/seg5 p2.4/seg7 p2.6/seg9 p4.3/seg11 p4.5/seg13 p3.0/seg15 p3.2/txd/seg17 n.c. n.c. n.c. 50-pin dip socket 1 3 5 7 9 11 13 15 17 19 21 23 25 27 29 31 33 35 37 39 41 43 45 47 49 2 4 6 8 10 12 14 16 18 20 22 24 26 28 30 32 34 36 38 40 42 44 46 48 50 j101 figure 22-4. 44-pin connector for tb9484/88 target board target system target cable for connector part name: as20d order code: sm6304 j101 1 2 49 50 1 2 49 50 50-pin connector 50-pin connector figure 22-5. s3c9484/c9488/f9488 probe adapter for 44-pin connector package

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